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1. 发明授权

US06782435B2 Device for spatially and temporally reordering for data between a processor, memory and peripherals 失效
标题翻译：用于在处理器，存储器和外围设备之间对数据进行空间和时间重新排序的设备
公开(公告)号：US06782435B2
公开(公告)日：2004-08-24
申请号：US09816066
申请日：2001-03-26
申请人： Serafin E. Garcia , Zohar B. Bogin , Steve Clohset , Mikal C. Hunsaker
发明人： Serafin E. Garcia , Zohar B. Bogin , Steve Clohset , Mikal C. Hunsaker
IPC分类号： G06F700
CPC分类号： G06F7/768
摘要： A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.
摘要翻译：空间和时间对数据进行处理器，存储器和外围设备的设备。该设备能够对来自存储器，外围设备和处理器的写入和读取操作的数据进行空间和时间重新排序。该设备使用外围写入路径空间重新排序单元和外围写入时间重排序单元来重新排列发送到外围设备和存储器的数据。此外，该设备使用外围读取数据路径空间重新排序单元来重新排序从外围设备读取的数据。此外，主存储器空间重排序单元用于重新排序从主存储器读取的数据。

2. 发明授权

US06910114B2 Adaptive idle timer for a memory device 失效
标题翻译：适用于存储设备的空闲定时器
公开(公告)号：US06910114B2
公开(公告)日：2005-06-21
申请号：US10298201
申请日：2002-11-15
申请人： Suryaprasad Kareenahalli , Zohar B. Bogin , Mihir D. Shah
发明人： Suryaprasad Kareenahalli , Zohar B. Bogin , Mihir D. Shah
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1689 , G06F12/0215
摘要： Embodiments of the present invention provide for adaptively tuning the memory idle timer value in real time. Selected memory idle clock cycles are sampled to dynamically determine an optimized memory idle timer value. To optimize latency during sampling, the number of page hits (NPH) and number of page misses (NPM) are multiplied by weighted values WPH and WPM, respectively, such that the weighted function (WPH*NPH)−(WPM*NPM) is maximized. The weight associated with a page miss (WPM) is greater than the weight associated with a page hit (WPH), resulting in a bigger penalty for a page miss than a page hit. The selected setting is continuously optimized.
摘要翻译：本发明的实施例提供了实时自适应地调整存储器空闲定时器值。选择的存储器空闲时钟周期被采样以动态地确定优化的存储器空闲定时器值。为了优化采样期间的等待时间，页面命中次数（N＆lt; PH＆lt; / SUB）和页错失次数（N＆lt; PM＆lt;＆lt;＆gt;）与加权值W < SUB＆gt;和W＆gt; PM＆lt;＆lt;＆lt;＆lt;＆lt;＆lt;＆lt;＆lt;＆lt; SUB> * N ）最大化。与页面未命中相关联的权重（W SUB PM）大于与页面命中相关联的权重（W＆lt; PH＆lt;＆lt;＆lt;＆lt;＆lt;＆lt;＆gt;），导致页错误的惩罚更大一个页面命中。所选设置不断优化。

3. 发明授权

US07080217B2 Cycle type based throttling 失效
标题翻译：循环类型的节流
公开(公告)号：US07080217B2
公开(公告)日：2006-07-18
申请号：US10404773
申请日：2003-03-31
申请人： Suryaprasad Kareenhalli , Zohar B. Bogin , Gautam Loonawat
发明人： Suryaprasad Kareenhalli , Zohar B. Bogin , Gautam Loonawat
IPC分类号： G06F12/14
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3275 , Y02D10/126 , Y02D10/13 , Y02D10/14
摘要： Machine-readable media, methods, and apparatus are described to monitor and throttle issuance of transactions. In some embodiments, transactions are monitored during a monitoring window based upon cycle type. In response to determining that a threshold has been exceeded during the monitoring window, issuance of transactions during a throttling window are limited to a budget. Further, transactions issued during the throttling window consume a portion of the budget that based upon their cycle type.
摘要翻译：描述了机器可读介质，方法和装置来监视和限制事务的发布。在一些实施例中，基于循环类型在监视窗口期间监视事务。响应于在监视窗口期间确定已经超过阈值，在限制窗口期间发送交易被限制在预算之内。此外，在节流窗口期间发出的交易消耗了一部分基于周期类型的预算。

4. 发明授权

US07269754B2 Method and apparatus for flexible and programmable clock crossing control with dynamic compensation 有权
标题翻译：用于灵活可编程时钟交叉控制与动态补偿的方法和装置
公开(公告)号：US07269754B2
公开(公告)日：2007-09-11
申请号：US10335418
申请日：2002-12-30
申请人： Sridhar Ramaswamy , Amit Bodas , Zohar B. Bogin , David E. Freker , Suryaprasad R. Kareenahalli
发明人： Sridhar Ramaswamy , Amit Bodas , Zohar B. Bogin , David E. Freker , Suryaprasad R. Kareenahalli
IPC分类号： G06F1/02
CPC分类号： G06F5/06 , G11C7/22 , G11C7/222
摘要： A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.
摘要翻译：公开了一种从源时钟到目的地时钟的时钟交叉的系统和方法。在一个实施例中，源时钟相位使能信号用于使得一组锁存器组件能够选择性地输入源时钟脉冲。锁存器组件的输出可以由多路复用器根据目的时钟的相位来选择。在另一个实施例中，可以将时间延迟传递到目的时钟域，并且可以通过多个目的地时钟周期时间周期来计算。在某些情况下，可以调整时间延迟以补偿时钟跨越处理中的更长的延迟。

5. 发明授权

US07058752B2 Hardware detected command-per-clock 失效
标题翻译：硬件检测每个时钟指令
公开(公告)号：US07058752B2
公开(公告)日：2006-06-06
申请号：US10749183
申请日：2003-12-30
申请人： Suryaprasad Kareenahalli , Zohar B. Bogin , Anoop Mukker
发明人： Suryaprasad Kareenahalli , Zohar B. Bogin , Anoop Mukker
IPC分类号： G06F12/00
CPC分类号： G06F13/1631
摘要： A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a chip select line coupled to the memory device. The command-per-clock detection unit checks to see whether only certain low-order bits of the address lines are toggling between the current and previous addresses. Additional copies of address lines for particular low-order bits are provided to the memory device to reduce loading on the low order bit address lines, allowing the low order bit address lines to toggle quickly in order to avoid the necessity of inserting a one clock period wait state. If the command-per-clock detection unit does not find a match (meaning that more than the low order address bits are toggling) then the wait state is inserted by deasserting the chip select line for a clock period.
摘要翻译：存储器控制器经由存储器通道耦合到存储器件。存储器控制器包括每时钟脉冲检测单元，其将当前地址的一部分与先前地址的一部分进行比较。如果存在匹配，则存储器控制器可以继续断言耦合到存储器件的芯片选择线。命令/时钟检测单元检查地址线的某些低位是否在当前地址和以前的地址之间切换。用于特定低位的地址线的附加副本被提供给存储器件以减少低位位地址线上的负载，允许低位位地址线快速切换，以避免插入一个时钟周期等待状态如果命令/时钟检测单元没有找到匹配（意味着比低位地址位多于切换），则通过在芯片选择线上断开时钟周期来插入等待状态。

6. 发明授权

US07047384B2 Method and apparatus for dynamic timing of memory interface signals 失效
标题翻译：存储器接口信号的动态定时的方法和装置
公开(公告)号：US07047384B2
公开(公告)日：2006-05-16
申请号：US10185497
申请日：2002-06-27
申请人： Amit Bodas , Zohar B. Bogin , David E. Freker , Suryaprasad Kareenahalli , Sridhar Ramaswamy
发明人： Amit Bodas , Zohar B. Bogin , David E. Freker , Suryaprasad Kareenahalli , Sridhar Ramaswamy
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F13/1689 , G06F13/4243
摘要： A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.
摘要翻译：一种用于使用不同定时来锁存由相同设计的两个存储器件发送的信号以补偿信号必须在其上传播的导体长度差异的方法和装置。

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