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1. 发明授权

US08828886B2 Low dielectric constant insulating film and method for forming the same 有权
标题翻译：低介电常数绝缘膜及其形成方法
公开(公告)号：US08828886B2
公开(公告)日：2014-09-09
申请号：US13440480
申请日：2012-04-05
申请人： Seiji Samukawa , Shigeo Yasuhara , Shingo Kadomura , Tsutomu Shimayama , Hisashi Yano , Kunitoshi Tajima , Noriaki Matsunaga , Masaki Yoshimaru
发明人： Seiji Samukawa , Shigeo Yasuhara , Shingo Kadomura , Tsutomu Shimayama , Hisashi Yano , Kunitoshi Tajima , Noriaki Matsunaga , Masaki Yoshimaru
IPC分类号： H01L21/312 , C09D183/04 , H01L21/02 , C23C16/48 , C23C16/40
CPC分类号： H01L21/02126 , C23C16/401 , C23C16/486 , H01L21/02216 , H01L21/02277
摘要： Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.
摘要翻译：公开了由包含Si原子，O原子，C原子和H原子的聚合物形成的低介电常数绝缘膜，其包括其中多个具有SiO结构的碱性分子在直链中键合的直链分子，粘合剂具有连接多个直链分子的SiO结构的分子。指示线性型SiO结构的信号的面积比为49％以上，表示Si（CH3）的信号的信号量为66％以上。

2. 发明申请

US20120190212A1 LOW DIELECTRIC CONSTANT INSULATING FILM AND METHOD FOR FORMING THE SAME 有权
标题翻译：低介电常数绝缘膜及其形成方法
公开(公告)号：US20120190212A1
公开(公告)日：2012-07-26
申请号：US13440480
申请日：2012-04-05
申请人： Seiji SAMUKAWA , Shigeo Yasuhara , Shingo Kadomura , Tsutomu Shimayama , Hisashi Yano , Kunitoshi Tajima , Noriaki Matsunaga , Masaki Yoshimaru
发明人： Seiji SAMUKAWA , Shigeo Yasuhara , Shingo Kadomura , Tsutomu Shimayama , Hisashi Yano , Kunitoshi Tajima , Noriaki Matsunaga , Masaki Yoshimaru
IPC分类号： H01L21/312 , C09D183/04
CPC分类号： H01L21/02126 , C23C16/401 , C23C16/486 , H01L21/02216 , H01L21/02277
摘要： Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.
摘要翻译：公开了由包含Si原子，O原子，C原子和H原子的聚合物形成的低介电常数绝缘膜，其包括其中多个具有SiO结构的碱性分子在直链中键合的直链分子，粘合剂具有连接多个直链分子的SiO结构的分子。指示线性型SiO结构的信号的面积比为49％以上，表示Si（CH3）的信号的信号量为66％以上。

3. 发明申请

US20050263247A1 Plasma processing apparatus and plasma processing method 审中-公开
标题翻译：等离子体处理装置和等离子体处理方法
公开(公告)号：US20050263247A1
公开(公告)日：2005-12-01
申请号：US11060598
申请日：2005-02-18
申请人： Seiji Samukawa , Satoshi Nishikawa , Shingo Kadomura
发明人： Seiji Samukawa , Satoshi Nishikawa , Shingo Kadomura
IPC分类号： H05H1/00 , C23F1/00 , G01R31/12 , H01J37/32 , H01L21/205 , H01L21/3065
CPC分类号： H01J37/32935 , G01R31/1263 , H01J2237/0206
摘要： In a plasma processing apparatus which includes a chamber (1) equipped with a wafer stage (3) for mounting thereon a substrate (2) to be processed, and which processes the substrate (2) by exposure to a plasma (4), a photon detection sensor (5) for measuring an ultraviolet-light-induced current is placed on a circumferential portion of a substrate mounting surface (3a) of the wafer stage (3) so that the occurrence of an abnormal discharge can be detected, in real time, from a change in the output of the photon detection sensor (5).
摘要翻译：在一种等离子体处理装置中，其包括配备有用于在其上安装待处理的基板（2）并通过暴露于等离子体（4）来处理基板（2）的晶片台（3）的室（1），将用于测量紫外光感应电流的光子检测传感器（5）放置在晶片台（3）的基板安装表面（3a）的周向部分上，从而可以检测出异常放电的发生来自光子检测传感器（5）的输出的变化的实时的。

4. 发明申请

US20090325328A1 Plasma processing apparatus and plasma processing method 审中-公开
标题翻译：等离子体处理装置和等离子体处理方法
公开(公告)号：US20090325328A1
公开(公告)日：2009-12-31
申请号：US12585119
申请日：2009-09-03
申请人： Seiji Samukawa , Satoshi Nishikawa , Shingo Kadomura
发明人： Seiji Samukawa , Satoshi Nishikawa , Shingo Kadomura
IPC分类号： H01L21/66
CPC分类号： H01J37/32935 , G01R31/1263 , H01J2237/0206
摘要： A plasma processing method is provided. The method includes providing photon detection sensors for measuring an ultraviolet-light-induced current around circumferential portions of a wafer stage within a plasma chamber. The method also includes providing a semiconductor wafer on the wafer stage and performing plasma processing so as to form an insulating layer the semiconductor wafer or etch an insulating layer formed on the semiconductor wafer.
摘要翻译：提供等离子体处理方法。该方法包括提供光子检测传感器，用于测量等离子体室内的晶片台周围的紫外光感应电流。该方法还包括在晶片台上提供半导体晶片并执行等离子体处理，以便形成半导体晶片的绝缘层或蚀刻形成在半导体晶片上的绝缘层。

5. 发明授权

US06391437B1 COMPOSITE MATERIAL AND MANUFACTURING METHOD THEREOF, SUBSTRATE PROCESSING APPARATUS AND MANUFACTURING METHOD THEREOF, SUBSTRATE MOUNTING STAGE AND MANUFACTURING METHOD THEREOF, AND SUBSTRATE PROCESSING METHOD 失效
标题翻译：复合材料及其制造方法，基板加工装置及其制造方法，基板安装阶段及其制造方法以及基板处理方法
公开(公告)号：US06391437B1
公开(公告)日：2002-05-21
申请号：US09015636
申请日：1998-01-29
申请人： Shingo Kadomura , Kei Takatsu , Shinsuke Hirano
发明人： Shingo Kadomura , Kei Takatsu , Shinsuke Hirano
IPC分类号： C09J502
CPC分类号： C04B37/006 , B32B18/00 , C04B35/111 , C04B35/195 , C04B35/565 , C04B35/581 , C04B35/652 , C04B35/803 , C04B37/026 , C04B41/009 , C04B41/52 , C04B2235/526 , C04B2235/5264 , C04B2237/062 , C04B2237/12 , C04B2237/121 , C04B2237/122 , C04B2237/123 , C04B2237/341 , C04B2237/343 , C04B2237/365 , C04B2237/366 , C04B2237/38 , C04B2237/62 , C04B2237/64 , C04B2237/68 , C04B2237/72 , Y10T428/249955 , Y10T428/249956 , C04B41/4521 , C04B41/4523 , C04B41/5155 , C04B41/4527 , C04B41/5031 , C04B41/5063 , C04B41/522 , C04B38/00
摘要： The invention provides a substrate processing apparatus using a composite material which permits avoidance of occurrence of damages caused by the difference in thermal expansion between different materials and can be with stand the use at high temperatures. The substrate processing apparatus for processing a substrate is partially (for example, a substrate mounting stage) composed of a composite material 11 consisting of a matrix 12 comprising a ceramics member made of, for example, cordierite ceramics, aluminum nitride and/or a texture filled with an aluminum-based material (for example, aluminum or aluminum and silicon), and a ceramics layer (comprising, for example, Al2O3 and/or AlN) provided on the surface of the matrix 12.
摘要翻译：本发明提供一种使用复合材料的基板处理装置，其能够避免由不同材料之间的热膨胀差引起的损害的发生，并且可以在高温下使用。用于处理基板的基板处理装置部分地（例如，基板安装台）由复合材料11组成，复合材料11由包括例如堇青石陶瓷，氮化铝和/或纹理的陶瓷构件的基体12组成填充有铝基材料（例如铝或铝和硅），以及设置在基体12的表面上的陶瓷层（包括例如Al 2 O 3和/或AlN）。

6. 发明授权

US5994226A Dry etching method 失效
标题翻译：干蚀刻法
公开(公告)号：US5994226A
公开(公告)日：1999-11-30
申请号：US712572
申请日：1996-09-13
申请人： Shingo Kadomura
发明人： Shingo Kadomura
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3213
CPC分类号： H01L21/32139
摘要： A dry etching method for a conductive material layer is disclosed. The dry etching method has the steps of: forming an oxygen-containing antireflection film on a surface of a conductive material layer; forming a patterned mask layer on the antireflection film; forming a sidewall protection film on a sidewall of the mask layer; and etching the conductive material layer using the mask layer having the sidewall protection film formed thereon. The sidewall protection film is formed after the antireflection film is patterned using the mask layer. The antireflection film is patterned after the sidewall protection film is formed, with the sidewall protection film left on the sidewall of the antireflection film. The sidewall protection film is formed by using at least one of sulfur based compound and sulfur nitride based compound. The antireflection film is composed of an SiON based material. The conductive material layer is composed of a material selected from the group consisting of a polycide film, an Al based alloy material layer, a Cu based alloy material layer and a refractory metal layer. The conductive material layer is formed on a semiconductor substrate having an insulating film formed on a surface thereof. The conductive material layer is formed on an insulating film having a barrier metal layer formed on a surface thereof.
摘要翻译：公开了一种用于导电材料层的干蚀刻方法。干蚀刻方法具有以下步骤：在导电材料层的表面上形成含氧抗反射膜; 在抗反射膜上形成图案化掩模层; 在所述掩模层的侧壁上形成侧壁保护膜; 并且使用其上形成有侧壁保护膜的掩模层蚀刻导电材料层。在使用掩模层对防反射膜进行图案化之后形成侧壁保护膜。在形成侧壁保护膜之后，防反射膜被图案化，侧壁保护膜留在防反射膜的侧壁上。通过使用硫系化合物和硫化氮类化合物中的至少一种来形成侧壁保护膜。防反射膜由SiON基材料构成。导电材料层由选自由多晶硅膜，Al基合金材料层，Cu基合金材料层和难熔金属层组成的组中的材料构成。导电材料层形成在其表面上形成有绝缘膜的半导体衬底上。导电材料层形成在其表面上形成有阻挡金属层的绝缘膜上。

7. 发明授权

US5962084A Plasma CVD process and semiconductor device having metal film formed by the process 失效
标题翻译：具有通过该方法形成的金属膜的等离子体CVD工艺和半导体器件
公开(公告)号：US5962084A
公开(公告)日：1999-10-05
申请号：US770819
申请日：1996-12-20
申请人： Takaaki Miyamoto , Shingo Kadomura , Atsushi Kawashima
发明人： Takaaki Miyamoto , Shingo Kadomura , Atsushi Kawashima
IPC分类号： C23C16/50 , C23C16/08 , C23C16/511 , H01L21/28 , H01L21/285 , H01L21/768 , H05H1/29
CPC分类号： H01L21/28556 , C23C16/08 , H01L21/76877
摘要： A plasma CVD process of forming a metal film containing a residual halogen element in a small amount and a high reliability semiconductor device fabricated by the process. The plasma CVD process includes the step of forming a metal film on a substrate to be processed, using a mixed gas containing a metal halide and hydrogen, wherein the plasma CVD process adopts a plasma CVD condition which is determined in such a manner that emission spectrum intensities of a plasma of the mixed gas are measured; and a mixing ratio of the metal halide in the mixed gas is set to be not more than a value at which a decreasing rate, depending on mixing of the metal halide, of an emission spectrum intensity of a hydrogen spectral line is rapidly changed and also at which an increasing ratio, depending on mixing of the metal halide, of an emission spectrum intensity of a halogen element is rapidly changed.
摘要翻译：形成含有少量残留卤素元素的金属膜和通过该工艺制造的高可靠性半导体器件的等离子体CVD工艺。等离子体CVD工艺包括使用包含金属卤化物和氢气的混合气体在待加工的基板上形成金属膜的步骤，其中等离子体CVD工艺采用等离子体CVD条件，该等离子体CVD条件以发射光谱测量混合气体的等离子体的强度; 并且将混合气体中的金属卤化物的混合比设定为不大于根据金属卤化物的混合使得氢谱线的发射光谱强度的降低速率迅速变化的值，其中取决于金属卤化物的混合，卤素元素的发射光谱强度的增加比率迅速变化。

8. 发明授权

US5599742A Interconnection forming method 失效
标题翻译：互连形成方法
公开(公告)号：US5599742A
公开(公告)日：1997-02-04
申请号：US933027
申请日：1992-08-20
申请人： Shingo Kadomura
发明人： Shingo Kadomura
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/318 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L21/467
CPC分类号： H01L21/76885 , H01L21/321 , Y10S438/902 , Y10S438/958
摘要： A method of forming interconnectors involves the passivation (surface protective) of aluminum interconnector patterns and connection hole surfaces without objectionable particle level problems. Under electrical discharge disassociation conditions, sulphur (S) is liberated and permits the formation of an anti-corrosive polythiazyl in a plasma generated by using gaseous sulphur and nitrogen containing compounds. For example, in order to prevent the exposure of an aluminum interconnector material layer to atmospheric air after it has been resist masked and etched, plasma CVD is used with a gas containing a mixture of S.sub.2 F.sub.2 /H.sub.2 /N.sub.2, to form a protective film on the surfaces of the pattern. In this coated condition, after corrosion is prevented until such time as the next fabrication step which forms an interlayer insulation membrane is carried out. The protective film can be removed by heating the wafer to about 150.degree. C. at which time the protective film readily sublimes or decomposes. Other application come in that, after a natural oxide film is removed from a contact hole surface, until an upper interconnector is formed, the above mentioned protective film is temporarily formed over the exposed surfaces to prevent the reformation of the natural oxide film.
摘要翻译：形成互连器的方法涉及铝互连器图案和连接孔表面的钝化（表面保护），而没有不利的粒子水平问题。在放电分解条件下，释放硫（S），并允许在通过使用气态含硫和含氮化合物产生的等离子体中形成抗腐蚀性的聚噻唑。例如，为了防止铝绝缘体材料层在其被抗蚀剂掩模蚀刻之后暴露于大气中，等离子体CVD与含有S2F2 / H2 / N2混合物的气体一起使用以形成保护膜图案的表面。在这种涂覆状态下，防止腐蚀，直到进行形成层间绝缘膜的下一个制造步骤为止。可以通过将晶片加热至约150℃来除去保护膜，此时保护膜容易升华或分解。另外的应用是，在从接触孔表面除去自然氧化物膜之后，直到形成上部互连器，上述保护膜暂时形成在露出的表面上，以防止天然氧化物膜的重整。

9. 发明授权

US5312518A Dry etching method 失效
标题翻译：干蚀刻法
公开(公告)号：US5312518A
公开(公告)日：1994-05-17
申请号：US891448
申请日：1992-05-29
申请人： Shingo Kadomura
发明人： Shingo Kadomura
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31144
摘要： A dry etching method whereby an SiO.sub.2 layer and an Si.sub.3 N.sub.4 layer may be etched with high selectivity for each other. As etching gas, such sulfur fluorides as S.sub.2 F.sub.2 are used which, when dissociated by electric discharges, will form SF.sub.x.sup.+ as a main etchant for the SiO.sub.2 layer or F* as a main etchant for the Si.sub.3 N.sub.4 layer and release sulfur in the plasma. When the SiO.sub.2 layer is etched on the Si.sub.3 N.sub.4 layer as an underlying layer via a resist mask, nitrogen atoms, removed from the underlying layer upon exposure thereof to the plasma, will combine with sulfur in the plasma to form on the exposed surface thereof such sulfur nitride compounds as polythiazyl (SN).sub.x, which will, in turn, serve to achieve high selectivity for the underlying layer. The SiO.sub.2 layer can also be etched via an Si.sub.3 N.sub.4 mask patterned into a predetermined shape, in which case sulfur nitride compounds formed on the Si.sub.3 N.sub.4 mask will serve to achieve high selectivity therefor.
摘要翻译：可以以高选择性彼此蚀刻SiO 2层和Si 3 N 4层的干蚀刻方法。作为蚀刻气体，使用如S2F2这样的硫化氟，当通过放电解离时，其将形成SF x +作为SiO 2层或F *的主要蚀刻剂，作为Si 3 N 4层的主要蚀刻剂并释放等离子体中的硫。当通过抗蚀剂掩模在Si 3 N 4层上作为下层蚀刻SiO 2层时，在暴露于等离子体时从底层去除的氮原子将与等离子体中的硫结合，以在暴露的表面上形成这样的硫氮化物作为聚噻吩（SN）x，其又将用于实现对下层的高选择性。也可以通过图案化为预定形状的Si 3 N 4掩模蚀刻SiO 2层，在这种情况下，形成在Si 3 N 4掩模上的硫化氮化合物将用于实现高选择性。

10. 发明授权

US5180464A Dry etching method 失效
标题翻译：干蚀刻方法
公开(公告)号：US5180464A
公开(公告)日：1993-01-19
申请号：US644014
申请日：1991-01-22
申请人： Tetsuya Tatsumi , Shingo Kadomura
发明人： Tetsuya Tatsumi , Shingo Kadomura
IPC分类号： H01L21/3213
CPC分类号： H01L21/32137
摘要： Disclosed is a dry etching method by which a polycide film consisting of a refractory metal silicide layer and a polysilicon layer are stacked one upon the other may be etched with high anisotropy, low pollution, high selectivity and high speed without using flon gases.According to the method of the present invention, an etching gas containing a fluorine base gas mixed at least with HBr is used for etching the polycide film for realizing anisotropic processing under sidewall protection by a reaction product of mainly the resist material and Br.Overetching for uniform processing in the wafer plane is performed with the use approximately solely of the fluorine base gas or HBr for realizing a high speed and improving substrate selectivity.The overetching step is preceded by oxygen plasma treatment for oxidizing the reaction product and intensifying side wall protective effects while improving anisotropy.Finally, the changes in the emission spectrum intensity during the etching are monitored for determining the end point of etching of the refractory metal silicide layer to enable more accurate setting of the etching conditions.

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