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1. 发明授权

US5349656A Task scheduling method in a multiprocessor system where task selection is determined by processor identification and evaluation information 失效
标题翻译：多处理器系统中的任务调度方法，其中任务选择由处理器识别和评估信息确定
公开(公告)号：US5349656A
公开(公告)日：1994-09-20
申请号：US797912
申请日：1991-11-26
申请人： Seiji Kaneko , Toshiyuki Kinoshita , Akio Yamamoto , Yasuhisa Tamura
发明人： Seiji Kaneko , Toshiyuki Kinoshita , Akio Yamamoto , Yasuhisa Tamura
IPC分类号： G06F15/16 , G06F9/46 , G06F9/48 , G06F9/50 , G06F15/177 , G06F9/445
CPC分类号： G06F9/4881
摘要： A task scheduling method for a multiprocessor in a computer system having a main storage unit and a plurality of instruction processors each having a buffer storage unit, the buffer storage unit having a copy of a part of the main storage unit and deleting a part of the copy when reading a main storage unit area not stored in the buffer storage unit. The task scheduling method is accomplished by providing each task control block of a task control block queue with an area for storing processor identification of an instruction processor which executes a task and an area for storing evaluation information for evaluating a copied data amount for the task, remaining in the buffer storage unit of the instruction processor executing the task; causing the instruction processor to register the processor identification and evaluation information in the task control block when execution of the task is stopped; and when selecting a task to be executed by a subject instruction processor from a plurality of tasks to be executed in the computer system, causing the subject instruction processor to sequentially read task control blocks in the task control block queue to check each task in accordance with the processor identification and evaluation information, and if a checked result shows that the copied data amount corresponding to a checked task and remaining in the buffer storage unit of the instruction processor is greater than a predetermined amount, causing the subject instruction processor not to select the checked task and allowing another instruction processor to select the checked task.
摘要翻译：一种具有主存储单元和多个指令处理器的计算机系统中的多处理器的任务调度方法，每个具有缓冲存储单元，所述缓冲存储单元具有所述主存储单元的一部分的副本，当读取未存储在缓冲存储单元中的主存储单元区域时复制。任务调度方法是通过为任务控制块队列的每个任务控制块提供用于存储执行任务的指令处理器的处理器标识的区域和用于存储用于评估该任务的复制数据量的评估信息的区域，剩余在执行任务的指令处理器的缓冲存储单元中; 使指令处理器在执行任务停止时将处理器识别和评估信息注册到任务控制块中; 并且当从计算机系统中要执行的多个任务中选择要由主体指令处理器执行的任务时，使得所述主题指令处理器顺序地读取任务控制块队列中的任务控制块，以根据处理器识别和评估信息，并且如果检查结果示出与检查任务相对应并且保留在指令处理器的缓冲存储单元中的复制数据量大于预定量，则使得对象指令处理器不选择检查任务并允许另一个指令处理器选择被检查的任务。

2. 发明授权

US5377341A Buffer storage control system 失效
标题翻译：缓冲存储控制系统
公开(公告)号：US5377341A
公开(公告)日：1994-12-27
申请号：US710336
申请日：1991-06-05
申请人： Seiji Kaneko , Toshiyuki Kinoshita , Akio Yamamoto , Yasuhisa Tamura
发明人： Seiji Kaneko , Toshiyuki Kinoshita , Akio Yamamoto , Yasuhisa Tamura
IPC分类号： G06F12/00 , G06F12/08 , G06F15/16 , G06F15/177 , G06F12/02
CPC分类号： G06F12/0855
摘要： In buffer storage equipment, storage control is carried out by a pipeline having two stages including a stage for executing out-of-order processing for processing a succeeding request with priority and a stage for not executing out-of-order processing. By this storage control, a request processing order is guaranteed at the stage for not executing out-of-order processing and a request is caused to wait at the stage for executing out-of-order processing.
摘要翻译：在缓冲存储设备中，通过具有两级的流水线进行存储控制，该流水线包括用于执行优先处理后续请求的无序处理的级和不执行无序处理的级。通过该存储控制，在阶段保证不执行无序处理的请求处理顺序，并且使请求在用于执行无序处理的阶段等待。

3. 发明授权

US5333289A Main memory addressing system 失效
标题翻译：主存储器寻址系统
公开(公告)号：US5333289A
公开(公告)日：1994-07-26
申请号：US703458
申请日：1991-05-21
申请人： Seiji Kaneko , Masaya Watanabe , Toshiyuki Kinoshita , Yasuhisa Tamura , Masaichiro Yoshioka
发明人： Seiji Kaneko , Masaya Watanabe , Toshiyuki Kinoshita , Yasuhisa Tamura , Masaichiro Yoshioka
IPC分类号： G06F11/00 , G06F12/06 , G11C29/00 , G06F12/00
CPC分类号： G06F11/1666 , G06F12/0607 , G06F11/20 , G06F2201/85 , G11C29/88
摘要： In a computer system having a main storage equipment comprising a plurality of storage equipments, the storage area of each storage equipment is divided in fixed units and an interleave mode is set for each of fixed nuts. When configuration of the main storage equipment is to be changed by disconnection or coupling of storage equipments, necessary data are moved and the interleave mode is changed for all data of the above described fixed unit.
摘要翻译：在具有包括多个存储设备的主存储设备的计算机系统中，每个存储设备的存储区域以固定单元划分，并且为每个固定螺母设置交错模式。当通过存储设备的断开或耦合来改变主存储设备的配置时，移动所需的数据，并且对于上述固定单元的所有数据改变交错模式。

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