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1. 发明授权

US6040110A Process and apparatus for the removal of resist 失效
标题翻译：去除抗蚀剂的方法和设备
公开(公告)号：US6040110A
公开(公告)日：2000-03-21
申请号：US129842
申请日：1998-08-06
申请人： Seiichirou Shirai , Toshihiko Onozuka , Takayuki Noishiki , Satoshi Sakai , Katsuhiro Sasajima , Eiji Toyoda , Makoto Namikawa
发明人： Seiichirou Shirai , Toshihiko Onozuka , Takayuki Noishiki , Satoshi Sakai , Katsuhiro Sasajima , Eiji Toyoda , Makoto Namikawa
IPC分类号： C09J7/00 , C09J5/00 , G03F7/34 , G03F7/42 , H01L21/027 , H01L21/311 , G03C11/12
CPC分类号： H01L21/31127 , G03F7/42 , G03F7/34
摘要： The present invention provides a process for the removal of a resist layer formed on a semiconductor substrate, which enables easy removal of a resist layer without causing any damage on a gate oxide layer, and an apparatus therefor. The process comprises the steps of forming a gate oxide layer on the semiconductor substrate; forming a resist layer as a resist pattern on the gate oxide layer; removing the gate oxide layer at unnecessary area utilizing the resist layer as a mask; applying a pressure-sensitive adhesive sheet to the semiconductor substrate such that the gate oxide layer left on the semiconductor substrate and the resist layer are masked, and peeling the pressure-sensitive adhesive sheet together with the resist layer off the semiconductor substrate to separate and remove the resist layer from the semiconductor substrate.
摘要翻译：本发明提供一种去除形成在半导体衬底上的抗蚀剂层的方法，其能够容易地除去抗蚀剂层而不会对栅极氧化物层造成任何损坏，以及其装置。该方法包括在半导体衬底上形成栅极氧化层的步骤; 在栅极氧化物层上形成作为抗蚀剂图案的抗蚀剂层; 使用抗蚀剂层作为掩模去除不需要的区域的栅极氧化物层; 将压敏粘合片施加到半导体衬底上，使得残留在半导体衬底上的栅极氧化物层和抗蚀剂层被掩蔽，并将压敏粘合片与抗蚀剂层一起剥离出半导体衬底以分离和去除来自半导体衬底的抗蚀剂层。

2. 发明授权

US5725971A Method of manufacturing phase shift masks and a method of manufacturing semiconductor integrated circuit devices 失效
标题翻译：制造相移掩模的方法和制造半导体集成电路器件的方法
公开(公告)号：US5725971A
公开(公告)日：1998-03-10
申请号：US600736
申请日：1996-02-13
申请人： Noboru Moriuchi , Seiichirou Shirai , Toshihiko Onozuka
发明人： Noboru Moriuchi , Seiichirou Shirai , Toshihiko Onozuka
IPC分类号： G03F1/29 , G03F1/68 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F7/70433 , G03F1/30 , G03F1/36 , G03F7/70283
摘要： A technique to minimize an increase in the design and manufacture times required for making phase shift masks is provided. The process of the technique involves preparing a hole unit cell comprising one target hole and auxiliary holes located close to the four sides of the target hole, and then laying out on first layout data first hole unit cells 26c.sub.1 -26c.sub.3 arranged in a certain orientation at a first pitch and second hole unit cells 27c.sub.1 -27c.sub.3 arranged in the same orientation at a second pitch, narrower than the first pitch. This process generates data of hole groups, each comprising the target hole and auxiliary holes on a first phase shift mask that is used in forming hole patterns in a resist film coated over the semiconductor substrate.
摘要翻译：提供了一种最小化制造相移掩模所需的设计和制造时间的技术。该技术的工艺包括制备一个孔单元，其包括一个目标孔和位于目标孔四侧附近的辅助孔，然后布置在以一定方向排列的第一布局数据上的第一孔单元26c1-26c3 第一间距和第二孔单元电池27c1-27c3以相对于第一间距的第二节距相同的方向排列。该过程产生孔组的数据，每个孔组包括用于形成涂覆在半导体衬底上的抗蚀剂膜中的孔图案的第一相移掩模上的目标孔和辅助孔。

3. 发明授权

US09390934B2 Phase shift mask, method of forming asymmetric pattern, method of manufacturing diffraction grating, and method of manufacturing semiconductor device 有权
$Phase shift mask, method of forming asymmetric pattern, method of manufacturing diffraction grating, and method of manufacturing semiconductor device$
标题翻译：相移掩模，不对称图案的形成方法，衍射光栅的制造方法以及制造半导体器件的方法
公开(公告)号：US09390934B2
公开(公告)日：2016-07-12
申请号：US14350314
申请日：2012-09-13
申请人： Kazuyuki Kakuta , Toshihiko Onozuka , Shigeru Matsui , Yoshisada Ebata , Norio Hasegawa
发明人： Kazuyuki Kakuta , Toshihiko Onozuka , Shigeru Matsui , Yoshisada Ebata , Norio Hasegawa
IPC分类号： G03F1/26 , H01L21/3065 , G03F1/30 , H01L21/308 , G03F1/00
CPC分类号： H01L21/3065 , G03F1/0046 , G03F1/26 , G03F1/28 , G03F1/30 , H01L21/3085
摘要： A technique of forming an asymmetric pattern by using a phase shift mask, and further, techniques of manufacturing a diffraction grating and a semiconductor device, capable of improving accuracy of a product and capable of shortening manufacturing time. In a method of manufacturing a diffraction grating by using a phase shift mask (in which a light shield part and a light transmission part are periodically arranged), light emitted from an illumination light source is transmitted through the phase shift mask, and a photoresist on a surface of a Si wafer is exposed by providing interference between zero diffraction order light and positive first diffraction order light which are generated by the transmission through this phase shift mask onto the surface of the Si wafer, and a diffraction grating which has a blazed cross-sectional shape is formed on the Si wafer.
摘要翻译：通过使用相移掩模形成非对称图案的技术，以及制造衍射光栅和半导体器件的技术，能够提高产品的精度并能缩短制造时间。在通过使用相移掩模（其中周期性地布置有遮光部分和透光部分）制造衍射光栅的方法中，从照明光源发射的光透射穿过相移掩模，并且光致抗蚀剂在通过提供由通过该相移掩模的透射产生的零衍射级光和正的第一衍射级光之间的干涉而暴露于Si晶片的表面到Si晶片的表面上的衍射光栅和具有闪耀十字在Si晶片上形成截面形状。

4. 发明申请

US20110140275A1 Semiconductor device and manufacturing method of the same 有权
公开(公告)号：US20110140275A1
公开(公告)日：2011-06-16
申请号：US12929782
申请日：2011-02-15
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L23/532
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

5. 发明申请

US20140092384A1 DIFFRACTION GRATING MANUFACTURING METHOD, SPECTROPHOTOMETER, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 审中-公开
标题翻译：衍射光栅制造方法，分光光度计和半导体器件制造方法
公开(公告)号：US20140092384A1
公开(公告)日：2014-04-03
申请号：US14118375
申请日：2012-05-17
申请人： Yoshisada Ebata , Shigeru Matsui , Norio Hasegawa , Kazuyuki Kakuta , Toshihiko Onozuka
发明人： Yoshisada Ebata , Shigeru Matsui , Norio Hasegawa , Kazuyuki Kakuta , Toshihiko Onozuka
IPC分类号： G02B5/18 , H01L21/26
CPC分类号： G02B5/1857 , G01J3/0262 , G01J3/18 , G01J3/42 , G02B5/18 , G02B5/1814 , G02B5/1861 , G03F1/50 , G03F1/54 , G03F7/0005 , H01L21/26
摘要： The present invention has been made in view of the above, and an object thereof is to provide a manufacturing technique capable of manufacturing a diffraction grating which is suitable for use in a spectrophotometer and has an apex angle of a convex portion of about 90° and can satisfy high diffraction efficiency and a low stray light amount. A method of manufacturing a diffraction grating, the method including: setting an exposure condition such that a sectional shape of a convex portion of a resist on a substrate, which has been formed by exposure, is an asymmetric triangle with respect to an opening portion shape of a mask having an opening portion with a periodic structure and an angle formed by a long side and a short side of the triangle is about 90°; and performing exposure.
摘要翻译：发明内容本发明是鉴于上述问题而完成的，其目的在于提供一种制造技术，其能够制造适用于分光光度计的衍射光栅，并具有约90°的凸部的顶角和可以满足高衍射效率和低杂散光量。一种制造衍射光栅的方法，该方法包括：设置曝光条件，使得通过曝光形成的基板上的抗蚀剂的凸部的截面形状相对于开口部形状为不对称三角形具有周期性结构的开口部分和由三角形的长边和短边形成的角度的面具为约90°; 并进行曝光。

6. 发明申请

US20120270390A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120270390A1
公开(公告)日：2012-10-25
申请号：US13541229
申请日：2012-07-03
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.
摘要翻译：在半导体器件中，铜互连之间的电容降低，并且同时提高绝缘击穿，并且通过包括以下步骤的制造方法采取不对准的对策：包括在绝缘膜上方形成包含铜作为主要成分的互连基板，形成绝缘膜和用于储存器图案的隔离绝缘膜，形成能够抑制或防止铜在互连的上表面和侧表面上以及在绝缘膜和绝缘膜上方形成的绝缘膜，形成绝缘膜的绝缘膜形成为使得相互连接的相对侧面上方的沉积速率大于其下方的沉积速率，以形成相邻互连之间的气隙，最后将绝缘膜平坦化膜层间CMP。

7. 发明申请

US20090142919A1 Semiconductor device and manufacturing method of the same 有权
公开(公告)号：US20090142919A1
公开(公告)日：2009-06-04
申请号：US12320357
申请日：2009-01-23
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

8. 发明授权

US07501347B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07501347B2
公开(公告)日：2009-03-10
申请号：US11446137
申请日：2006-06-05
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L21/311
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.
摘要翻译：在半导体器件中，铜互连之间的电容降低，并且同时提高绝缘击穿，并且通过包括以下步骤的制造方法采取不对准的对策：包括在绝缘膜上方形成包含铜作为主要成分的互连基板，形成绝缘膜和用于储存器图案的隔离绝缘膜，形成能够抑制或防止铜在互连的上表面和侧表面上以及在绝缘膜和绝缘膜上方形成的绝缘膜，形成绝缘膜的绝缘膜形成为使得相互连接的相对侧面上方的沉积速率大于其下方的沉积速率，以形成相邻互连之间的气隙，最后将绝缘膜平坦化膜层间CMP。

9. 发明申请

US20140302679A1 PHASE SHIFT MASK, METHOD OF FORMING ASYMMETRIC PATTERN, METHOD OF MANUFACTURING DIFFRACTION GRATING, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：相位移掩模，形成非对称图案的方法，制造衍射光栅的方法和制造半导体器件的方法
公开(公告)号：US20140302679A1
公开(公告)日：2014-10-09
申请号：US14350314
申请日：2012-09-13
申请人： Kazuyuki Kakuta , Toshihiko Onozuka , Shigeru Matsui , Yoshisada Ebata , Norio Hasegawa
发明人： Kazuyuki Kakuta , Toshihiko Onozuka , Shigeru Matsui , Yoshisada Ebata , Norio Hasegawa
IPC分类号： H01L21/3065 , G03F1/26 , H01L21/308
CPC分类号： H01L21/3065 , G03F1/0046 , G03F1/26 , G03F1/28 , G03F1/30 , H01L21/3085
摘要： A technique of forming an asymmetric pattern by using a phase shift mask, and further, techniques of manufacturing a diffraction grating and a semiconductor device, capable of improving accuracy of a product and capable of shortening manufacturing time. In a method of manufacturing a diffraction grating by using a phase shift mask (in which a light shield part and a light transmission part are periodically arranged), light emitted from an illumination light source is transmitted through the phase shift mask, and a photoresist on a surface of a Si wafer is exposed by providing interference between zero diffraction order light and positive first diffraction order light which are generated by the transmission through this phase shift mask onto the surface of the Si wafer, and a diffraction grating which has a blazed cross-sectional shape is formed on the Si wafer.
摘要翻译：通过使用相移掩模形成非对称图案的技术，以及制造衍射光栅和半导体器件的技术，能够提高产品的精度并能缩短制造时间。在通过使用相移掩模（其中周期性地布置有遮光部分和透光部分）制造衍射光栅的方法中，从照明光源发射的光透射穿过相移掩模，并且光致抗蚀剂在通过提供由通过该相移掩模的透射产生的零衍射级光和正的第一衍射级光之间的干涉而暴露于Si晶片的表面到Si晶片的表面上的衍射光栅和具有闪耀十字在Si晶片上形成截面形状。

10. 发明授权

US08247902B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08247902B2
公开(公告)日：2012-08-21
申请号：US12929782
申请日：2011-02-15
申请人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
发明人： Junji Noguchi , Takashi Matsumoto , Takayuki Oshima , Toshihiko Onozuka
IPC分类号： H01L23/48
CPC分类号： H01L21/7682 , H01L21/76811 , H01L21/76832 , H01L21/76834 , H01L21/76843
摘要： In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.
摘要翻译：在半导体器件中，铜互连之间的电容降低，并且同时提高绝缘击穿，并且通过包括以下步骤的制造方法采取不对准的对策：包括在绝缘膜上方形成包含铜作为主要成分的互连基板，形成绝缘膜和用于储存器图案的隔离绝缘膜，形成能够抑制或防止铜在互连的上表面和侧表面上以及在绝缘膜和绝缘膜上方形成的绝缘膜，形成绝缘膜的绝缘膜形成为使得相互连接的相对侧面上方的沉积速率大于其下方的沉积速率，以形成相邻互连之间的气隙，最后将绝缘膜平坦化膜层间CMP。

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