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    • 10. 发明授权
    • Computer system having two DMA circuits assigned to the same address space
    • 具有分配给相同地址空间的两个DMA电路的计算机系统
    • US06209042B1
    • 2001-03-27
    • US09122283
    • 1998-07-24
    • Takashi YanagisawaMasayoshi TaniguchiMasayoshi Nakano
    • Takashi YanagisawaMasayoshi TaniguchiMasayoshi Nakano
    • G06F300
    • G06F13/28
    • A computer system has a central processing unit (“CPU”) and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal (“IRDY”), a device select signal (“DEVSEL”) and a target ready signal (“TRDY”). First and second direct memory access devices (“DMA”) are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.
    • 计算机系统具有中央处理单元(“CPU”)和多个外围设备。 总线连接CPU和外围设备。 命令信号通过总线发送,包括启动器就绪信号(“IRDY”),设备选择信号(“DEVSEL”)和目标就绪信号(“TRDY”)。 第一和第二直接存储器访问设备(“DMA”)连接到总线并分配相同的地址空间。 第一和第二开关分别选择性地连接和断开从第一和第二DMA设备输出的DEVSEL和TRDY信号。 控制器逻辑接收DEVSEL和TRDY信号,并指示第一和第二开关的打开和关闭。