专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07451417B1 Timing annotation accuracy through the use of static timing analysis tools 有权
标题翻译：定时注释精度通过使用静态时序分析工具
公开(公告)号：US07451417B1
公开(公告)日：2008-11-11
申请号：US11433127
申请日：2006-05-12
申请人： Scott J. Campbell , Mario Escobar , Jaime D. Lujan , Walter A. Manaker, Jr. , Brian D. Philofsky
发明人： Scott J. Campbell , Mario Escobar , Jaime D. Lujan , Walter A. Manaker, Jr. , Brian D. Philofsky
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.
摘要翻译：一种产生电路设计的定时信息的方法可以包括确定用于电路设计的静态定时数据，并且识别在电路设计的功能仿真中使用的定时信息源。该方法还可以包括更新定时信息源以包括静态定时数据的至少一部分。

2. 发明授权

US07421675B1 Annotating timing information for a circuit design for increased timing accuracy 有权
标题翻译：注释电路设计的时序信息，提高定时精度
公开(公告)号：US07421675B1
公开(公告)日：2008-09-02
申请号：US11333863
申请日：2006-01-17
申请人： Scott J. Campbell , Mario Escobar , Jaime D. Lujan , Walter A. Manaker, Jr. , Brian D. Philofsky
发明人： Scott J. Campbell , Mario Escobar , Jaime D. Lujan , Walter A. Manaker, Jr. , Brian D. Philofsky
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the minimum clock path delay for a destination register of the circuit design. The method further can include adjusting a register timing parameter for the destination register according to the difference and performing a timing verification on the destination register using the adjusted register timing parameter.
摘要翻译：注意用于执行定时分析的电路设计的定时信息的方法可以包括确定用于电路设计的寄存器的最小和最大时钟路径延迟，以及计算目的寄存器的目的地寄存器的最大时钟路径延迟和最小时钟路径延迟之间的差异电路设计。该方法还可以包括根据差值调整目的地寄存器的寄存器定时参数，并使用经调整的寄存器定时参数在目的地寄存器上执行定时验证。

3. 发明授权

US07653677B1 Digital logic circuit for adding three binary words and method of implementing same 有权
标题翻译：用于添加三个二进制字的数字逻辑电路及其实现方法
公开(公告)号：US07653677B1
公开(公告)日：2010-01-26
申请号：US11044744
申请日：2005-01-26
申请人： Scott J. Campbell , Brian D. Philofsky , Lyman D. Lewis
发明人： Scott J. Campbell , Brian D. Philofsky , Lyman D. Lewis
IPC分类号： G06F7/50
CPC分类号： G06F7/509
摘要： A digital logic circuit includes at least one stage. Each stage includes sum logic, combinatorial logic, and carry chain logic. The sum logic is configured to generate a first sum signal from a first set of three input signals. The combinatorial logic includes a carry generation portion and a sum generation portion. The carry generation portion is configured to generate a first carry signal from a second set of three input signals. The sum generation portion is configured to generate a second sum signal from the first sum signal and the first carry signal. The carry chain logic is configured to process the first sum signal, the second sum signal, and a carry-in signal to generate a carry-out signal and a third sum signal.
摘要翻译：数字逻辑电路包括至少一个级。每个阶段包括和逻辑，组合逻辑和进位链逻辑。总和逻辑被配置为从第一组三个输入信号产生第一和信号。组合逻辑包括进位产生部分和和产生部分。进位产生部分被配置为从第三组输入信号产生第一进位信号。和产生部分被配置为从第一和信号和第一进位信号产生第二和信号。进位链逻辑被配置为处理第一和信号，第二和信号和进位信号以产生进位信号和第三和信号。

4. 发明授权

US08146041B1 Latch based optimization during implementation of circuit designs for programmable logic devices 有权
标题翻译：实现可编程逻辑器件电路设计时的基于锁存器的优化
公开(公告)号：US08146041B1
公开(公告)日：2012-03-27
申请号：US13180782
申请日：2011-07-12
申请人： Sankaranarayanan Srinivasan , Sridhar Krishnamurthy , Brian D. Philofsky , Kamal Chaudhary , Anirban Rahut
发明人： Sankaranarayanan Srinivasan , Sridhar Krishnamurthy , Brian D. Philofsky , Kamal Chaudhary , Anirban Rahut
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.
摘要翻译：实现可编程逻辑器件内的电路设计的计算机实现的方法可以包括选择电路设计的至少一个电路元件。所选择的电路元件可以被转换成锁存器。在将所选择的电路元件转换为锁存器之后，可以在电路设计上执行时序分析。当电路设计的时序改善时，计算机可以确定电路设计的时序是否改善，并且可以接受所选择的电路元件到锁存器的转换。可以输出电路设计。

5. 发明授权

US08104012B1 System and methods for reducing clock power in integrated circuits 有权
标题翻译：集成电路中降低时钟功率的系统和方法
公开(公告)号：US08104012B1
公开(公告)日：2012-01-24
申请号：US12363721
申请日：2009-01-31
申请人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
发明人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/62
摘要： Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.
摘要翻译：在诸如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD）的可编程逻辑器件（PLD）中实现动态功率节省和资源的有效利用，通过接收指定包括时钟信号，时钟缓冲器的电路的设计网表，时钟使能信号和同步元件，检查设计网表以识别耦合到公共时钟和时钟使能信号的同步元件，将时钟信号切割到同步元件以形成修改后的设计网表，将门控时钟缓冲器插入修改的网表以输出门控时钟信号到同步元件，响应于时钟使能信号，并在修改的网表上执行放置和布线。提供了一种用于在EDA工具上执行该方法的系统。可以将这些方法提供为存储在计算机可读介质上的可执行指令，其使可编程处理器执行该方法。

6. 发明授权

US08010923B1 Latch based optimization during implementation of circuit designs for programmable logic devices 有权
标题翻译：实现可编程逻辑器件电路设计时的基于锁存器的优化
公开(公告)号：US08010923B1
公开(公告)日：2011-08-30
申请号：US12128335
申请日：2008-05-28
申请人： Sankaranarayanan Srinivasan , Sridhar Krishnamurthy , Brian D. Philofsky , Kamal Chaudhary , Anirban Rahut
发明人： Sankaranarayanan Srinivasan , Sridhar Krishnamurthy , Brian D. Philofsky , Kamal Chaudhary , Anirban Rahut
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F17/505
摘要： A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.
摘要翻译：实现可编程逻辑器件内的电路设计的计算机实现的方法可以包括选择电路设计的至少一个电路元件。所选择的电路元件可以被转换成锁存器。在将所选择的电路元件转换为锁存器之后，可以在电路设计上执行时序分析。当电路设计的时序改善时，可以确定电路设计的时序是否改善，并且可以接受所选择的电路元件到锁存器的转换。可以输出电路设计。

7. 发明授权

US07274211B1 Structures and methods for implementing ternary adders/subtractors in programmable logic devices 有权
标题翻译：在可编程逻辑器件中实现三元加法器/减法器的结构和方法
公开(公告)号：US07274211B1
公开(公告)日：2007-09-25
申请号：US11373700
申请日：2006-03-10
申请人： James M. Simkins , Brian D. Philofsky
发明人： James M. Simkins , Brian D. Philofsky
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17728 , G06F7/5057 , G06F7/509
摘要： Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.
摘要翻译：在可编程逻辑器件（PLD）中实现加法器电路的结构和方法。 PLD包括双输出查找表（LUT）和其他可编程逻辑元件。加法器电路包括将三个输入总线映射成两个压缩总线的3：2（3至2）压缩器电路，以及将两个压缩总线相加以产生最终总和的2输入级联加法器电路。双输出LUT实现3：2压缩器电路和2输入加法器的一部分。使用PLD的附加可编程逻辑元件来实现2输入加法器的剩余部分。在一些实施例中，3：2压缩器电路之前是M：3压缩器，其将3输入加法器改变为M输入加法器。在这些实施例中，第二输入总线相对于第一输入总线左移，第三输入总线相对于第二输入总线左移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式