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1. 发明授权

US5511025A Write per bit with write mask information carried on the data path past the input data latch 失效
标题翻译：通过输入数据锁存器在数据路径上承载的写入掩码信息来写入每位
公开(公告)号：US5511025A
公开(公告)日：1996-04-23
申请号：US361901
申请日：1994-12-21
申请人： Scott E. Smith , Duy-Loan T. Le , Michael Ho
发明人： Scott E. Smith , Duy-Loan T. Le , Michael Ho
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1078
摘要： A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.
摘要翻译：动态随机存取存储器部分30通过将相应的写入屏蔽信息锁存器118定位在相应的本地I / O缓冲器116附近来提供每位写入特征。因此，写入掩码信息通过数据锁存器108并跨越数据路径到达被锁存之前的本地I / O缓冲器116。这减少了另外写入掩码引线所需的面积，在x8，x16，x32或x64位元件中可能不能容纳较大的写入掩码引线。

2. 发明授权

US5402390A Fuse selectable timing signals for internal signal generators 失效
标题翻译：保险丝可选择内部信号发生器的定时信号
公开(公告)号：US5402390A
公开(公告)日：1995-03-28
申请号：US130977
申请日：1993-10-04
申请人： Duc Ho , Duy-Loan T. Le , Kenneth A. Poteet , Scott E. Smith
发明人： Duc Ho , Duy-Loan T. Le , Kenneth A. Poteet , Scott E. Smith
IPC分类号： G11C11/406 , G11C11/4076 , G11C7/00
CPC分类号： G11C11/406 , G11C11/4076
摘要： Switching circuits controlled by a fuse that can be blown after testing the DRAM part select the timing signals coupled from a binary counter to internal signal generator circuits. The internal Circuits control self refresh in this embodiment. The decision to leave the fuse intact or blow the fuse rests on the test results obtained from each part and can vary depending upon maturity of the manufacturing process, the pause test results obtained and whether a low power part is desired. The fuse is affected after fabrication of the chip and at the same time as other fuses used for redundancy. This provides another degree of freedom in the manufacture of integrated circuits.
摘要翻译：通过在测试DRAM部件之后可以熔断的熔丝控制的开关电路选择从二进制计数器耦合到内部信号发生器电路的定时信号。在本实施例中，内部电路控制自刷新。保险丝完好无损或者熔断保险丝的决定取决于从每个部件获得的测试结果，并且可以根据制造过程的成熟度，所获得的暂停测试结果以及是否需要低功率部件而变化。保险丝在制造芯片后受到影响，同时与其他用于冗余的保险丝相同。这在集成电路的制造中提供了另一个自由度。

3. 发明授权

US5469385A Output buffer with boost from voltage supplies 失效
标题翻译：输出缓冲器，从电源提升
公开(公告)号：US5469385A
公开(公告)日：1995-11-21
申请号：US60323
申请日：1993-05-11
申请人： Scott E. Smith , Duy-Loan T. Le , Michael C. Stephens, Jr. , Masayoshi Nomura
发明人： Scott E. Smith , Duy-Loan T. Le , Michael C. Stephens, Jr. , Masayoshi Nomura
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1057 , G11C7/1051
摘要： An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.
摘要翻译： MOS DRAM存储器件包括具有N沟道输出晶体管的输出缓冲器，该N沟道输出晶体管必须接收升压的栅极信号以在输出端产生完整的Vdd输出高逻辑电平信号。 N沟道晶体管连接在Vdd电源电压和输出端子之间。输出缓冲器将Vdd电源电压连接到输出晶体管的栅极，短时间足以使栅极升高到Vdd电压电平，然后断开Vdd电源。然后，缓冲器将Vdd +电源电压连接到栅极，以将栅极电压增加至少一个高于Vdd电源电压的晶体管阈值。这提供了输出端子的Vdd电压。

4. 发明授权

US5410510A Process of making and a DRAM standby charge pump with oscillator having fuse selectable frequencies 失效
标题翻译：具有熔断器可选择频率的振荡器的制造过程和DRAM备用电荷泵
公开(公告)号：US5410510A
公开(公告)日：1995-04-25
申请号：US131067
申请日：1993-10-04
申请人： Scott E. Smith , Duy-Loan T. Le , Kenneth A. Poteet , Michael V. D. Ho
发明人： Scott E. Smith , Duy-Loan T. Le , Kenneth A. Poteet , Michael V. D. Ho
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C29/02 , G11C29/44 , G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C11/406 , G11C11/4074 , G11C29/02 , G11C29/44 , G11C29/50 , G11C29/50012 , G11C5/145 , G11C11/401
摘要： An oscillator (108) for a standby charge pump (102,104)in a dynamic random access memory part (30) includes a fuse (136). The fuse can be blown after testing the part while selecting redundant memory cells to reduce the frequency of the oscillator and obtain a lower power part. The oscillator (108) also drives the on-chip self-refresh circuits (106) that operate slower in response to the reduced frequency. Selecting redundant circuits also includes eliminating memory cells that pass the pause test, but by only a certain margin. Reducing the frequency of the oscillator driving the self-refresh circuits would otherwise cause failure of the cells that pass the pause test by only the certain margin. The oscillator circuit includes a ring of inverter stages (112) and a fused voltage bias circuit (110) generating one or another set of bias voltages (118,120) to the ring oscillator to alter its frequency of oscillation.
摘要翻译：用于动态随机存取存储器部分（30）中的备用电荷泵（102,104）的振荡器（108）包括熔丝（136）。在选择冗余存储单元之后，可以在测试该部件之后对熔丝进行熔断，以降低振荡器的频率并获得较低的功率部分。振荡器（108）还驱动响应于降低的频率而运行较慢的片上自刷新电路（106）。选择冗余电路还包括消除通过暂停测试但只有一定余量的存储单元。驱动自刷新电路的振荡器的频率降低将导致仅通过暂停测试的单元的故障。振荡器电路包括一个反相器级环（112）和熔断电压偏置电路（110），该电路产生一个或另一组偏置电压（118,120）给环形振荡器，以改变其振荡频率。

5. 发明授权

US06242936B1 Circuit for driving conductive line and testing conductive line for current leakage 有权
标题翻译：用于驱动导线的电路和测试导线用于漏电
公开(公告)号：US06242936B1
公开(公告)日：2001-06-05
申请号：US09366232
申请日：1999-08-03
申请人： Michael Duc Ho , Duy-Loan T. Le , Scott E. Smith
发明人： Michael Duc Ho , Duy-Loan T. Le , Scott E. Smith
IPC分类号： G01R3126
CPC分类号： G01R31/3004
摘要： A circuit (100) that drives word lines and tests a word line (102) in a semiconductor device is disclosed. A charge circuit (108) couples a supply voltage (VPP) to a charge node (106) according to a potential at a boot node (110). The charge node (106) supplies a charge voltage for the word line (102). In a standard cycle, the boot node (110) is charged to a high voltage, and maintained at the high potential, to keep the word line (102) charged. In a test cycle, the boot node (110) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (106) and the word line (102). In the event the word line (102) suffers from current leakage, a drop in potential will be detected at the charge rode (106).
摘要翻译：公开了一种在半导体器件中驱动字线并测试字线（102）的电路（100）。充电电路（108）根据引导节点（110）处的电位将电源电压（VPP）耦合到充电节点（106）。充电节点（106）为字线（102）提供充电电压。在标准周期中，引导节点（110）被充电到高电压并保持在高电位，以保持字线（102）充电。在测试周期中，引导节点（110）被充电到高电压，然后被放电到低电压，从而隔离充电节点（106）和字线（102）。在字线（102）遇到电流泄漏的情况下，在充电路径（106）处将检测到电位下降。

6. 发明授权

US06201752B1 Timing circuit for high voltage testing 有权
标题翻译：高电压测试定时电路
公开(公告)号：US06201752B1
公开(公告)日：2001-03-13
申请号：US09398240
申请日：1999-09-20
申请人： Anh Bui , Scott E. Smith , Duy-Loan T. Le
发明人： Anh Bui , Scott E. Smith , Duy-Loan T. Le
IPC分类号： G11C700
CPC分类号： C07H13/06 , C07H15/18 , C07H17/08 , C07H19/16 , G11C5/143 , G11C7/1072 , G11C11/401 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： A circuit is designed with a detector circuit (700) coupled between a supply voltage terminal (705) and a reference voltage terminal (755). The detector circuit produces a first control signal in response to a detected mode and produces a second control signal in response to another mode. A first circuit (205, 207) including a delay circuit receives the first control signal and a third control signal. The delay circuit produces a fourth control signal at an output terminal (215) in response to the first and third control signals. A second circuit (203) receives the second control signal and the third control signal. The second circuit produces the fourth control signal at the output terminal in response to the second and third control signals.
摘要翻译：电路设计有耦合在电源电压端（705）和参考电压端（755）之间的检测器电路（700）。检测器电路响应于检测模式产生第一控制信号，并且响应于另一模式产生第二控制信号。包括延迟电路的第一电路（205,207）接收第一控制信号和第三控制信号。延迟电路响应于第一和第三控制信号在输出端（215）产生第四控制信号。第二电路（203）接收第二控制信号和第三控制信号。第二电路响应于第二和第三控制信号在输出端产生第四控制信号。

7. 发明授权

US6038177A Data pipeline interrupt scheme for preventing data disturbances 有权
标题翻译：用于防止数据干扰的数据流水线中断方案
公开(公告)号：US6038177A
公开(公告)日：2000-03-14
申请号：US253848
申请日：1999-02-22
申请人： M. Kumar Rajith , Kallol Mazumder , Scott E. Smith , Duy-Loan T. Le
发明人： M. Kumar Rajith , Kallol Mazumder , Scott E. Smith , Duy-Loan T. Le
IPC分类号： G11C7/10 , G11C16/04 , G11C8/00
CPC分类号： G11C7/1039 , G11C7/1051
摘要： A read mask circuit (300) is disclosed. A mask command is shifted through a series of mask latches (308 and 310) to generate the output-enable input (OE.sub.--) of an output driver (306). In synchronism with the mask command, data bits are shifted through a series of data latches (312 and 314) to the data input (DIN) of the output driver (306). To prevent a race condition between the mask command and the data bit that is to be masked (B3), the mask command, when latched in the second-to-last mask latch (308), is used to interrupt the last data latch (314). This prevents the to-be-masked data bit (B3) from being latched in the last data latch (314) and generating an undesirable output data transition by the output driver (306).
摘要翻译：公开了一种读掩模电路（300）。屏蔽命令通过一系列掩码锁存器（308和310）移位，以产生输出驱动器（306）的输出使能输入（OE-）。与掩模命令同步，数据位通过一系列数据锁存器（312和314）移动到输出驱动器（306）的数据输入（DIN）。为了防止掩码命令和要被屏蔽的数据位之间的竞争条件（B3），当锁存在第二到最后掩码锁存器（308）中时，掩码命令用于中断最后的数据锁存器 314）。这防止了被屏蔽的数据位（B3）被锁存在最后的数据锁存器（314）中，并且由输出驱动器（306）产生不期望的输出数据转换。

8. 发明授权

US5295101A Array block level redundancy with steering logic 失效
标题翻译：具有转向逻辑的阵列块级冗余
公开(公告)号：US5295101A
公开(公告)日：1994-03-15
申请号：US829124
申请日：1992-01-31
申请人： Michael C. Stephens, Jr. , Scott E. Smith , Charles J. Pilch , Duy-Loan T. Le , Terry T. Tsai , Arthur R. Piejko
发明人： Michael C. Stephens, Jr. , Scott E. Smith , Charles J. Pilch , Duy-Loan T. Le , Terry T. Tsai , Arthur R. Piejko
IPC分类号： G11C11/401 , G06F11/10 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/81 , G11C29/88 , G06F11/1008
摘要： The described embodiments of the present invention provide a circuit and method for a two level redundancy scheme for a semiconductor memory device. The memory device has one or more data blocks (12) with each data block (12) having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks (14) with each sub-block having a plurality of the memory cells. The first level redundancy scheme includes a few redundant elements for each sub-block for the replacement of defective elements, as is common in many modern semiconductor devices. The second level redundancy scheme includes at least one redundant sub-block of memory cells as part of the main memory for a fully functional memory device or, as an extra level of redundancy for at least one sub-block of memory cells containing defects which are not repairable using the redundant elements. When activated for redundancy, the second level redundancy scheme replaces at least one defective sub-block of memory devices with a like number of redundant sub-blocks of memory devices.
摘要翻译：本发明的所描述的实施例提供了一种用于半导体存储器件的二级冗余方案的电路和方法。存储器件具有一个或多个数据块（12），每个数据块（12）具有沿着行线和列线布置在可寻址行和列中的存储单元阵列。每个阵列被配置成子块（14），每个子块具有多个存储单元。第一级冗余方案包括用于替换缺陷元件的每个子块的少数冗余元件，这在许多现代半导体器件中是常见的。第二级冗余方案包括作为用于全功能存储器件的主存储器的一部分的存储器单元的至少一个冗余子块，或者作为包含缺陷的至少一个存储器单元子块的冗余级别不可修复使用冗余元素。当被激活用于冗余时，第二级冗余方案用存储器设备的相同数目的冗余子块替换至少一个存储器件的有缺陷子块。

9. 发明授权

US5706234A Testing and repair of wide I/O semiconductor memory devices designed for testing 失效
标题翻译：测试和修复设计用于测试的宽I / O半导体存储器件
公开(公告)号：US5706234A
公开(公告)日：1998-01-06
申请号：US766705
申请日：1996-12-13
申请人： Charles J. Pilch, Jr. , Carl W. Perrin , Duy-Loan T. Le , Scott E. Smith , Yutaka Komai
发明人： Charles J. Pilch, Jr. , Carl W. Perrin , Duy-Loan T. Le , Scott E. Smith , Yutaka Komai
IPC分类号： G01R31/28 , G11C29/00 , G11C29/34 , G11C29/44
CPC分类号： G11C29/34 , G11C29/44
摘要： A semiconductor memory device 40 includes an array of storage cells 130, addressable by row and column and specifically designed for testing. Row and column addresses are decoded to access a row and plural columns simultaneously. A test data bit to be written into the storage cells is replicated and stored into as many storage cells at once as there are columns simultaneously accessed. Upon readout for a comparison test, plural occurrences of the stored test data bit are compared with each other and with an expected data bit within parallel comparator circuitry 140 located within the memory device. A pass/fail signal (on lead 170) from the parallel comparator circuitry is transmitted to the memory device tester 30 for final defect analysis and correction. When a failure/defect is detected, information representing the address and the type of failure are stored in the memory device tester. A memory device test method also is described.
摘要翻译：半导体存储器件40包括可由行和列寻址并且被专门设计用于测试的存储单元阵列130。行和列地址被解码以同时访问行和多列。将要写入存储单元的测试数据位复制并存储到同一数量的存储单元中，因为存在列同时访问。在读出比较测试时，将存储的测试数据位的多次出现彼此进行比较，并与位于存储器件内的并行比较器电路140内的预期数据位进行比较。来自并行比较器电路的通过/失败信号（在引线170上）传送到存储器件测试器30用于最终的缺陷分析和校正。当检测到故障/缺陷时，表示地址和故障类型的信息存储在存储器件测试器中。还描述了存储器件测试方法。

10. 发明申请

US20180072635A1 Composting Apparatus 审中-公开
公开(公告)号：US20180072635A1
公开(公告)日：2018-03-15
申请号：US15266190
申请日：2016-09-15
申请人： Scott E. Smith
发明人： Scott E. Smith
IPC分类号： C05F17/02 , C05F9/02 , C05F17/00
CPC分类号： C05F17/0205 , C05F9/02 , C05F17/0045 , C05F17/0258 , C05F17/027 , Y02P20/145 , Y02W30/43
摘要： A cylindrical container or vessel, for example a pail, includes a bi-directionally rotatable internal auger having a rotation axis extending across a diameter of the shaft and manually-rotated by a handle outside the container, and tines extending in a radial direction of the shaft and arranged to turn and loosen contents of the container. The tines have different lengths and a predetermined relative spacing along the shaft, and be arranged extend at different angles, in order to maximize an amount of matter moved by the tines when rotating the shaft. The container may be vented to optimize aeration.

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