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1. 发明授权

US5889982A Method and apparatus for generating event handler vectors based on both operating mode and event type 失效
标题翻译：基于操作模式和事件类型生成事件处理程序向量的方法和装置
公开(公告)号：US5889982A
公开(公告)日：1999-03-30
申请号：US498696
申请日：1995-07-01
申请人： Scott Dion Rodgers , Rohit Vidwans , Joel Huang , Michael A. Fetterman , Kamla Huck
发明人： Scott Dion Rodgers , Rohit Vidwans , Joel Huang , Michael A. Fetterman , Kamla Huck
IPC分类号： G06F9/48 , G06F9/00
CPC分类号： G06F9/4812
摘要： A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is generated therefrom, for example, by referencing a lookup table. The microcode event handler vector is then used for invoking a microcode event handler to handle occurrence of these events in the processor. By the formation of an event vector, and the microcode event handler vector, execution performance is increased due to avoiding conditional branching within the processor, such as modem high performance architectures, including those which execute instructions in and out-of-order.
摘要翻译：一种处理事件的方法和装置，例如在处理器中发生的事件。通过组合指示处理器中的事件类型的事件类型信息和指示处理器的操作模式的模式信息来形成事件向量。例如，通过引用查找表来生成微代码事件处理程序向量。然后，微代码事件处理程序向量用于调用微代码事件处理程序来处理处理器中这些事件的发生。通过形成事件向量和微代码事件处理程序向量，由于避免了处理器内的条件分支，诸如调制解调器高性能体系结构（包括执行执行指令和无序执行指令）的执行性能增加。

2. 发明授权

US5664137A Method and apparatus for executing and dispatching store operations in a computer system 失效
标题翻译：用于在计算机系统中执行和调度存储操作的方法和装置
公开(公告)号：US5664137A
公开(公告)日：1997-09-02
申请号：US525499
申请日：1995-09-07
申请人： Jeffrey M. Abramson , Haitham Akkary , Atig A. Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Joel Huang , Kris G. Konigsfeld , Paul D. Madland , Prem Pahlajrai
发明人： Jeffrey M. Abramson , Haitham Akkary , Atig A. Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Joel Huang , Kris G. Konigsfeld , Paul D. Madland , Prem Pahlajrai
IPC分类号： G06F9/312 , G06F9/38 , G06F9/00
CPC分类号： G06F9/3889 , G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for performing store operations that includes calculating the address and obtaining the data for the store operation. The address represents the memory location to which the data is to be stored. Once the address is calculated and the data obtained, the store operation is committed to processor state. The store operation may be dispatched to memory to complete the execution of the store operation.
摘要翻译：一种用于执行存储操作的方法和装置，包括计算地址并获得用于存储操作的数据。地址表示要存储数据的存储器位置。一旦计算了地址并获得了数据，存储操作就被提交到处理器状态。可以将存储操作调度到存储器以完成存储操作的执行。

3. 发明授权

US6101597A Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor 失效
标题翻译：用于流水线处理器中依赖操作的最大吞吐量调度的方法和装置
公开(公告)号：US6101597A
公开(公告)日：2000-08-08
申请号：US176370
申请日：1993-12-30
申请人： Robert P. Colwell , Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Robert P. Colwell , Michael A. Fetterman , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3824 , G06F9/383
摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM). Before an instruction is executed and its result data written back, the storage location address of the result is provided to the CAM and associatively compared with the source operand addresses stored therein. A CAM match and its accompanying match bit indicate that the result of the instruction to be executed will provide a source operand to the dependent instruction waiting in the reservation station. Using a bypass mechanism, if the operand is computed after dispatch of the dependent instruction, then the source operand is provided directly from the execution unit computing the source operand to a source operand input of the execution unit executing the dependent instruction.
摘要翻译：通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。这两个操作通过多个机制来实现。用于确定源操作数的可用性以及因此用于发送到可用执行单元的依赖指令的准备的机制依赖于在操作数本身实际计算之前源操作数的可用性的预期确定执行另一条指令。指令的源操作数的存储地址存储在内容可寻址存储器（CAM）中。在执行指令并且其结果数据被写回之前，将结果的存储位置地址提供给CAM并与存储在其中的源操作数地址相关联地进行比较。 CAM匹配及其伴随的匹配位指示要执行的指令的结果将为在保留站等待的从属指令提供源操作数。使用旁路机制，如果在分派依赖指令之后计算操作数，则将操作数从执行单元直接提供到计算源操作数到执行依赖指令的执行单元的源操作数输入。

4. 发明授权

US5987600A Exception handling in a processor that performs speculative out-of-order instruction execution 失效
标题翻译：处理器中执行异常指令执行的异常处理
公开(公告)号：US5987600A
公开(公告)日：1999-11-16
申请号：US851140
申请日：1997-05-05
申请人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
发明人： David B. Papworth , Glenn J. Hinton , Michael A. Fetterman , Robert P. Colwell , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3865 , G06F9/3842 , G06F9/3863
摘要： A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.
摘要翻译：用于协调处理器中的异常的方法和电路。处理器为每个指令生成结果数据值和异常数据值，其中异常数据值指定相应指令是否引起异常。处理器以顺序程序顺序将结果数据值提交给处理器的架构状态，并且如果异常由异常数据值之一指示，则提取异常处理程序来处理异常。如果在结果数据值提交到处理器的架构状态时检测到异步事件，处理器将获取异步事件处理程序来处理异步事件。

5. 发明授权

US5717882A Method and apparatus for dispatching and executing a load operation to memory 失效
标题翻译：用于调度和执行对存储器的加载操作的方法和装置
公开(公告)号：US5717882A
公开(公告)日：1998-02-10
申请号：US764643
申请日：1996-12-11
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth , Michael A. Fetterman
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth , Michael A. Fetterman
IPC分类号： G06F9/312 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3836
摘要： A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.
摘要翻译：一种用于使用计算机系统中的处理器执行操作的方法和装置。通过使用调度管道和存储器执行管线来执行加载操作。调度管道调度处理器执行的加载操作，而存储器执行流水线控制对存储器的加载操作的执行。本发明通过在执行加载操作期间耦合两条管线的执行来减少执行加载操作所涉及的延迟。

6. 发明授权

US5627985A Speculative and committed resource files in an out-of-order processor 失效
标题翻译：乱序处理器中的投机和承诺资源文件
公开(公告)号：US5627985A
公开(公告)日：1997-05-06
申请号：US177244
申请日：1994-01-04
申请人： Michael A. Fetterman , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , Robert P. Colwell
发明人： Michael A. Fetterman , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , Robert P. Colwell
IPC分类号： G06F9/38 , G06F9/34
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.
摘要翻译：一种推测执行乱序处理器，包括一个包含多个物理寄存器的重排序电路，该多个物理寄存器缓冲整数和浮点运算的推测执行结果，以及一个包含多个提交状态寄存器的实际寄存器电路，该寄存器电路缓冲任一整数的提交执行结果或浮点运算，具体取决于寄存器。重排序和实际寄存器电路读取输入微操作的推测和确定的源数据值，并通过公共数据路径将推测和承诺的源数据值传输到微操作调度电路。退出逻辑电路通过将推测执行结果从重新排序电路传送到实际寄存器电路来将推测执行结果提交到架构状态。

7. 发明授权

US5604878A Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path 失效
标题翻译：避免共享共同回写路径的执行单元之间的回写冲突的方法和装置
公开(公告)号：US5604878A
公开(公告)日：1997-02-18
申请号：US513679
申请日：1995-08-01
申请人： Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Robert W. Martell , David B. Papworth
发明人： Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , Robert W. Martell , David B. Papworth
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3873 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.
摘要翻译：执行可能参与回写冲突的功能单位的管道延长，以避免冲突。提供逻辑电路用于比较两个并发执行的执行单元管线的深度，以确定冲突是否会发展。当看来两个执行单元将尝试同时回写时，将指示具有较短流水线的执行单元向其流水线添加一个阶段，将其结果存储在一个时钟周期的延迟缓冲器中。冲突解决后，延长给定功能单位管道的指示将被撤销。多级执行单元被设计为用信号通知保留站来延迟各种指令的发送以避免执行单元之间的冲突。

8. 发明授权

US5584037A Entry allocation in a circular buffer 失效
标题翻译：循环缓冲区中的条目分配
公开(公告)号：US5584037A
公开(公告)日：1996-12-10
申请号：US571377
申请日：1995-12-13
申请人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
发明人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
IPC分类号： G06F5/10 , G06F5/14 , G06F9/38 , G06F12/00
CPC分类号： G06F5/14 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.
摘要翻译：分配器为循环缓冲区分配条目。分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。分配器具有用于执行无序调度和推测执行的微处理器的应用。分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

9. 发明授权

US5574871A Method and apparatus for implementing a set-associative branch target buffer 失效
公开(公告)号：US5574871A
公开(公告)日：1996-11-12
申请号：US177155
申请日：1994-01-04
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

10. 发明授权

US5564111A Method and apparatus for implementing a non-blocking translation lookaside buffer 失效
标题翻译：用于实现非阻塞转换后备缓冲器的方法和装置
公开(公告)号：US5564111A
公开(公告)日：1996-10-08
申请号：US315833
申请日：1994-09-30
申请人： Andrew F. Glew , Haitham Akkary , Robert P. Colwell , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman
发明人： Andrew F. Glew , Haitham Akkary , Robert P. Colwell , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman
IPC分类号： G06F9/38 , G06F11/00 , G06F12/10 , G06F11/34
CPC分类号： G06F9/3865 , G06F11/0751 , G06F12/1027 , G06F9/3842 , G06F2212/684
摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.
摘要翻译：描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。所存储的信息包括指令的线性地址和识别指令年龄的信息。除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。然后，一个分支被带入微码。微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。系统被刷新，微代码仅对实际退出的故障指令执行。因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。本文描述了方法和装置实现。

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