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1. 发明授权

US07140767B2 Programmable ideality factor compensation in temperature sensors 有权
标题翻译：温度传感器可编程理想因子补偿
公开(公告)号：US07140767B2
公开(公告)日：2006-11-28
申请号：US10979437
申请日：2004-11-02
申请人： Scott C. McLeod , Thomas R. Anderson , Steven Burstein , Leonid A. Bekker
发明人： Scott C. McLeod , Thomas R. Anderson , Steven Burstein , Leonid A. Bekker
IPC分类号： G01K19/00 , G01K7/00
CPC分类号： G01K1/028 , G01K7/01
摘要： A temperature sensor circuit and system providing accurate readings using a temperature diode whose ideality factor may fall within a determined range. In one set of embodiments a change in diode junction voltage (ΔVBE) proportional to the temperature of the diode is captured and provided to an ADC, which may perform required signal conditioning functions on ΔVBE, and provide a numeric value output corresponding to the temperature of the diode. Errors in the measured temperature that might result from using diodes with ideality factors that differ from an expected ideality factor may be eliminated by programming the system to account for differing ideality factors. The gain of the temperature sensor may be matched to the ideality factor of the temperature diode by using an accurate, highly temperature stable reference voltage of the ADC to set the gain of the temperature measurement system. The reference voltage may have a trim capability to change the gain setting voltage by a digital address comprising a determined number of bits, with the programmable range for the reference voltage corresponding to a determined range of ideality factors.
摘要翻译：温度传感器电路和系统使用温度二极管提供精确的读数，其理想因素可能落在一个确定的范围内。在一组实施例中，与二极管的温度成比例的二极管结电压（DeltaV BAT）的变化被捕获并提供给ADC，ADC可以在DeltaV BE上执行所需的信号调节功能并且提供对应于二极管的温度的数值输出。可能通过对系统进行编程以解决不同的理想因素，消除可能由使用具有理想因素而不同于预期理想因素的二极管产生的测量温度的误差。通过使用ADC的精确，高度温度稳定的参考电压来设置温度测量系统的增益，温度传感器的增益可以与温度二极管的理想系数匹配。参考电压可以具有修整能力，以通过包括确定数量的位的数字地址来改变增益设置电压，其中参考电压的可编程范围对应于所确定的理想因素范围。

2. 发明授权

US07433790B2 Automatic reference voltage trimming technique 有权
标题翻译：自动参考电压调整技术
公开(公告)号：US07433790B2
公开(公告)日：2008-10-07
申请号：US11145906
申请日：2005-06-06
申请人： Thomas R. Anderson , William Castellano , Scott C. McLeod
发明人： Thomas R. Anderson , William Castellano , Scott C. McLeod
IPC分类号： G01D21/00
CPC分类号： G01R31/31703 , G01R31/3167
摘要： In one set of embodiments, trimming of a reference, which may be a bandgap reference and which is configured on an integrated circuit, may be controlled by an algorithm executed by logic circuitry also configured on the integrated circuit. The bandgap reference may be configured to generate a reference voltage provided to an analog to digital converter (ADC) comprised in a temperature sensor that may also be configured on the integrated circuit. The logic circuitry may be configured to execute one or more of a variety of test algorithms, for example a Successive Approximation Method or remainder processing, that are operable to adjust values of reference trim bits used in trimming the bandgap reference. A tester system configured to perform testing of the integrated circuit may initiate execution of the test algorithm, thereby initiating the trimming process, and may wait for the test algorithm to complete within a previously defined amount of time, or may poll the logic circuitry to determine when the trimming process is complete.
摘要翻译：在一组实施例中，可以通过由集成电路上也配置的逻辑电路执行的算法来控制可以是带隙基准并且在集成电路上配置的参考的修整。带隙基准可以被配置为产生提供给也可以在集成电路上配置的温度传感器中的模数转换器（ADC）的参考电压。逻辑电路可以被配置为执行各种测试算法中的一个或多个，例如连续逼近方法或余数处理，其可操作以调整在修整带隙基准中使用的参考修整位的值。配置为执行集成电路的测试的测试器系统可以启动测试算法的执行，从而启动修剪过程，并且可以等待测试算法在先前定义的时间量内完成，或者可以轮询逻辑电路以确定修剪过程完成。

3. 发明授权

US08558530B2 Low power regulator 有权
标题翻译：低功率调节器
公开(公告)号：US08558530B2
公开(公告)日：2013-10-15
申请号：US13110317
申请日：2011-05-18
申请人： Srinivas K. Pulijala , Scott C. McLeod
发明人： Srinivas K. Pulijala , Scott C. McLeod
IPC分类号： G05F3/16
CPC分类号： G05F1/56
摘要： A voltage regulator may derive current from a bias circuitry having a constant-transconductance. The bias circuitry may generate the bias current using three NMOS devices. The temperature coefficient of the bias current may be within a specified, desired range. The bias current may be mirrored to low-power regulator circuitry to bias a diode-connected transistor in the low-power regulator circuitry to operate in the strong inversion region. A ratioed current based on the output load current may be injected into a bipolar junction transistor (BJT) device to cause the gate-source voltage (VGS) of the diode-connected device to track the VGS of the output transistor of the voltage regulator, to ensure tighter load regulation. By operating the diode-connected transistor in strong inversion, by maintaining its (VGS) constant over temperature, and by cancelling the VGS of the output transistor of the voltage regulator with the base-emitter voltage (VBE) of the BJT device, the regulated voltage output may become free of the effects of temperature and supply voltage.
摘要翻译：电压调节器可以从具有恒定跨导的偏置电路获得电流。偏置电路可以使用三个NMOS器件产生偏置电流。偏置电流的温度系数可以在规定的期望范围内。偏置电流可以被镜像到低功率调节器电路，以将低功率调节器电路中的二极管连接的晶体管偏置以在强反转区域中操作。基于输出负载电流的比电流可以被注入到双极结型晶体管（BJT）器件中，以使二极管连接的器件的栅源电压（VGS）跟踪电压调节器的输出晶体管的VGS，以确保更严格的负载调节。通过在强反转中操作二极管连接的晶体管，通过使其（VGS）的温度保持恒定，并且通过用BJT器件的基极 - 发射极电压（VBE）消除电压调节器的输出晶体管的VGS，电压输出可能没有温度和电源电压的影响。

4. 发明授权

US08237449B2 Bi-directional high side current sense measurement 有权
标题翻译：双向高边电流检测测量
公开(公告)号：US08237449B2
公开(公告)日：2012-08-07
申请号：US12788896
申请日：2010-05-27
申请人： Madan G. Rallabandi , Scott C. McLeod
发明人： Madan G. Rallabandi , Scott C. McLeod
IPC分类号： G01R31/08
CPC分类号： G01R19/10 , G01R1/203
摘要： A system for measuring a voltage drop between two nodes in an electrical circuit, comprising a switched capacitor integrator (SCI), a comparator and a counter. The SCI alternately (a) captures charge onto a set of sampling capacitors and (b) selectively accumulates/transfers the charge onto a pair of integration capacitors, where the charge includes a first portion that is based on the voltage drop and a second portion that depends on a digital indicator signal. The comparator generates the digital indicator signal based on whether an analog output of the SCI is positive or negative. The counter counts a number of ones occurring in the digital indicator signal during a measurement interval. At the end of the measurement interval, the count value represents a measure of the voltage drop. Knowing the resistance between the two nodes, the voltage drop may be converted into a current measurement.
摘要翻译：一种用于测量电路中两个节点之间的电压降的系统，包括开关电容积分器（SCI），比较器和计数器。 SCI交替地（a）将电荷捕获到一组采样电容器上，并且（b）选择性地将电荷累积/传送到一对积分电容器，其中电荷包括基于电压降的第一部分和第二部分，取决于数字指示灯信号。比较器根据SCI的模拟输出是正还是负，产生数字指示信号。在测量间隔期间，计数器对数字指示信号中发生的数目进行计数。在测量间隔结束时，计数值表示电压降的度量。知道两个节点之间的电阻，电压降可以转换为电流测量。

5. 发明授权

US07893670B2 Frequency compensation scheme for stabilizing the LDO using external NPN in HV domain 有权
标题翻译：用于在HV域中稳定LDO使用外部NPN的频率补偿方案
公开(公告)号：US07893670B2
公开(公告)日：2011-02-22
申请号：US12389581
申请日：2009-02-20
申请人： Srinivas K. Pulijala , Scott C. McLeod
发明人： Srinivas K. Pulijala , Scott C. McLeod
IPC分类号： G05F1/00
CPC分类号： G05F1/575
摘要： A voltage regulator may comprise a regulator output configured to provide a regulated voltage, which may be controlled by an error amplifier based on the regulated voltage and a reference voltage. The error amplifier may control a source-follower stage to mirror a multiple of the current flowing in the source-follower stage into an internal pass device. A voltage developed by the mirror current may control an external pass device configured to deliver the load current into the regulator output. A first resistor may be configured to decouple a load capacitor coupled between the regulator output and reference ground, when the load current is below a specified value. A second resistor may be configured to create a bias current in the internal pass device even when the external pass device is close to cut-off region. A third resistor may be configured to counter the effects of negative impedance at the control terminal of the external pass device caused by the current-gain of the external pass device. A compensation capacitor and resistor may be coupled in series between the output of the error amplifier and the output of the voltage regulator to provide frequency compensation for the Miller-Effect.
摘要翻译：电压调节器可以包括被配置为提供调节电压的调节器输出，其可以由基于调节电压和参考电压的误差放大器控制。误差放大器可以控制源极跟随器级将在源极跟随器级中流动的电流的倍数镜像成内部通过器件。由反射镜电流产生的电压可以控制配置成将负载电流传递到调节器输出中的外部通过装置。当负载电流低于规定值时，第一电阻器可以被配置为去耦耦合在调节器输出端和参考地之间的负载电容器。第二电阻器可以被配置为在内部通路器件中产生偏置电流，即使当外部通过器件接近截止区域时。第三电阻器可以被配置为对抗由外部通过器件的电流增益引起的外部通过器件的控制端子处的负阻抗的影响。补偿电容器和电阻器可以串联耦合在误差放大器的输出端和电压调节器的输出端之间，为米勒效应提供频率补偿。

6. 发明申请

US20090322351A1 Adaptive Capacitive Sensing 审中-公开
标题翻译：自适应电容感测
公开(公告)号：US20090322351A1
公开(公告)日：2009-12-31
申请号：US12367336
申请日：2009-02-06
申请人： Scott C. McLeod
发明人： Scott C. McLeod
IPC分类号： G01R27/26 , G06F15/00 , G06F3/045
CPC分类号： G06F3/044 , G06F3/0416 , H03K17/002 , H03K17/962 , H03K2217/96075
摘要： A capacitive sensing circuit may comprise an RC (resistive-capacitive) bridge circuit, with a switching signal simultaneously applied to a reference path, and a signal path comprising the capacitance to be detected. Small perturbations in the capacitance may be detected by mixing/correlating a difference signal representative of the difference between the reference path signal and the signal path signal, to the switching signal. The output of the mixer may be filtered to virtually eliminate all EMI signals. A narrowband approach may also allow filtering of unwanted signals, enabling operation in systems susceptible to high levels of noise. Frequency stepping of the switching signal may minimize inband signal interference, and allow operation in the presence of many signals that would otherwise result in failure of the sensing circuit. Pad calibration may be implemented to free the user from a need to characterize each button channel capacitance and tailor the operation for each channel.
摘要翻译：电容感测电路可以包括RC（电阻 - 电容）桥接电路，其中切换信号同时施加到参考路径，以及包括要检测的电容的信号路径。可以通过将表示参考路径信号和信号路径信号之间的差的差分信号混合/相关到切换信号来检测电容中的微小扰动。可以对混频器的输出进行滤波以实际消除所有EMI信号。窄带方法还可以允许对不需要的信号进行滤波，使得能够在易受高水平噪声的系统中进行操作。切换信号的频率步进可以使带内信号干扰最小化，并允许存在否则会导致感测电路故障的许多信号的操作。可以实施垫校准以使用户不需要表征每个按钮通道电容并且调整每个通道的操作。

7. 发明申请

US20090237117A1 ELECTRICAL PHYSICAL LAYER ACTIVITY DETECTOR 有权
标题翻译：电气物理层活动检测器
公开(公告)号：US20090237117A1
公开(公告)日：2009-09-24
申请号：US12050223
申请日：2008-03-18
申请人： Scott C. McLeod
发明人： Scott C. McLeod
IPC分类号： H03K5/00
CPC分类号： H03F3/3076 , H03F3/45
摘要： A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be fully rectified through the output devices of the two buffers, and may be filtered to provide the detected output. The two buffers may be configured in a symmetrical structure that allows for the rejection of common-mode signals when the outputs of the buffers are coupled to a common node.
摘要翻译：低电流差分信号活动检测器电路可以被配置为在差分输入线上抑制大的共模信号，同时仍然检测到施加到同一组差分输入线的较小的差分信号。检测器电路可以包括在缓冲器输入处被驱动并且通过差分输入信号在缓冲器输出处被驱动的跨线性缓冲器。因此驱动检测器电路的输入的差分信号可以通过缓冲器输出装置进行半波整流，并且可以被滤波以提供检测的输出。当应用共模信号时，缓冲器的输入和输出可以彼此跟踪，并且在输出设备中不会纠正电流，从而提供共模信号抑制。检测器电路还可以配置有两个缓冲器，其具有耦合到公共节点的输出，每个缓冲器输入由差分输入信号中的相应一个驱动。由此驱动检测器电路的输入的差分信号可以通过两个缓冲器的输出装置完全整流，并且可以被滤波以提供检测到的输出。两个缓冲器可以配置成对称结构，当缓冲器的输出耦合到公共节点时允许抑制共模信号。

8. 发明申请

US20090220219A1 Delta-Sigma Modulator for a Fan Driver 有权
标题翻译：用于风扇驱动器的Delta-Sigma调制器
公开(公告)号：US20090220219A1
公开(公告)日：2009-09-03
申请号：US12040554
申请日：2008-02-29
申请人： Scott C. McLeod , Chao-Ming Tsai
发明人： Scott C. McLeod , Chao-Ming Tsai
IPC分类号： H02P7/285
CPC分类号： H02P7/285
摘要： A fan driver circuit for powering a fan with a linear voltage may be designed using digital design techniques, resulting in a testable, accurate circuit on a smaller die size. The fan driver circuit may be configured to receive a digital control signal, which may be a sequence of numeric values, e.g. multiple-bit binary numbers, each indicative of a desired present rotational speed of the fan. The fan driver circuit may be implemented using a digital modulator, e.g. a delta-sigma modulator, with a simple low-pass filter, e.g. an RC-filter at the output, and may use oversampling based on a system clock, to shift in-band noise to out-of-band frequencies, and digital interpolation to filter out unwanted images from the upsampled digital control signal. The delta-sigma modulator may be constructed as a first-order delta-sigma modulator using an error-feedback structure to reduce die size.
摘要翻译：可以使用数字设计技术设计用于为线性电压供电的风扇的风扇驱动器电路，从而在较小的管芯尺寸上产生可测试的精确电路。风扇驱动器电路可以被配置为接收数字控制信号，数字控制信号可以是数字序列的序列，例如。多位二进制数，每个指示风扇的期望的当前转速。风扇驱动器电路可以使用数字调制器来实现，例如，具有简单的低通滤波器的Δ-Σ调制器，例如。输出端的RC滤波器，并且可以使用基于系统时钟的过采样来将带内噪声移位到带外频率，以及数字内插以从上采样的数字控制信号滤除不需要的图像。 Δ-Σ调制器可以被构造为使用误差反馈结构来减小管芯尺寸的一阶Δ-Σ调制器。

9. 发明授权

US5179359A Digitally controlled frequency generator including a crystal oscillator 失效
标题翻译：数字控制频率发生器，包括晶体振荡器
公开(公告)号：US5179359A
公开(公告)日：1993-01-12
申请号：US851724
申请日：1992-03-16
申请人： Scott C. McLeod
发明人： Scott C. McLeod
IPC分类号： H03B21/02
CPC分类号： H03B21/02
摘要： A digitally controlled oscillator (100) having a first oscillator circuit (108) for providing an oscillator signal F.sub.o of a defined frequency and a digital divider (110) for dividing the oscillator signal F.sub.o by a selectable number controlled by a digital word for providing a clock signal F.sub.clk. A second oscillator circuit (104) receives the clock signal F.sub.clk and provides a low frequency signal F.sub.c. The second oscillator circuit includes a digitally controlled resonator element (112) for determining the frequency of the low frequency signal and has a center frequency dependent upon the clock signal. Circuitry (118, 120, 138) is included for providing first and second pairs of quadrature phase shifted signals derived from the clock signal F.sub.clk and the low frequency signal F.sub.c and from the oscillator signal F.sub.o, respectively. Finally, a mixer (136) is provided for mixing the first and second pairs of quadrature phase shifted signals for providing a single high frequency output signal F.sub.out which varies in accordance with the digital word.
摘要翻译：一种数字控制振荡器（100），具有用于提供定义频率的振荡器信号Fo的第一振荡器电路（108）和数字分频器（110），用于将振荡器信号Fo除以由数字字控制的可选数量，以提供时钟信号Fclk。第二振荡器电路（104）接收时钟信号Fclk并提供低频信号Fc。第二振荡器电路包括用于确定低频信号的频率并且具有取决于时钟信号的中心频率的数字控制谐振元件（112）。包括电路（118,120,138），用于提供从时钟信号Fclk和低频信号Fc以及从振荡器信号Fo得到的第一和第二对正交相移信号。最后，提供混合器（136），用于混合第一和第二对正交相移信号，以提供根据数字字变化的单个高频输出信号Fout。

10. 发明申请

US20120094463A1 High-Density Capacitor Configured On a Semiconductor 有权
标题翻译：高密度电容配置在半导体
公开(公告)号：US20120094463A1
公开(公告)日：2012-04-19
申请号：US13303318
申请日：2011-11-23
申请人： Scott C. McLeod
发明人： Scott C. McLeod
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.
摘要翻译：半导体器件上的开关电容器电路可以包括精确匹配的高密度金属 - 金属电容器，使用顶板到底板条纹电容来获得所需的电容值。多晶硅板可以插入底部金属层的下面，并且自举到每个电容器的顶板，以便最小化和/或消除寄生顶板对衬底电容。这可以释放用于形成额外的边缘电容的底部金属层，从而增加电容密度。通过仅根据从顶板到底板的边缘电容形成每个电容，不使用平行板电容，这可以减少电容器失配。也可以消除对衬底的寄生的底板电容，仅剩余的自举多晶硅板的电容仅为小电容器可以通过将每个电容器的顶板耦合到包括在其中的放大器的差分输入中的相应一个开关电容电路。

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