专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060121858A1 Sigma delta transmitter circuits and transceiver using the same 失效
标题翻译： Sigma Delta发射机电路和收发器使用相同
公开(公告)号：US20060121858A1
公开(公告)日：2006-06-08
申请号：US11207003
申请日：2005-08-19
申请人： Satoshi Tanaka , Kazuyuki Hori , Manabu Kawabe , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Satoshi Tanaka , Kazuyuki Hori , Manabu Kawabe , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H04B1/40 , H04B1/02
CPC分类号： H04B1/406 , H04B1/0003
摘要： A ΣΔ transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90°, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.
摘要翻译：即使在多个频带中工作的情况下，也可以将环路滤波器LF，电荷泵电流和其他因素设定为相同条件的SigmaDelta发送器，因此允许部件数量减少，同时使能要提供用于接收的本地信号的相位之间的角度接近正好90°，这是确保对元件间变化的鲁棒性并因此适合于大规模集成的特征。将VCO的振荡频率设定为发送频率的偶数倍，经由分频器生成发送信号。根据调制信号的幅度分量来改变增益的装置被添加到其输入是来自VCO的信号的放大器，并且由此使得涉及幅度调制（例如EDGE）的调制信号的传输成为可能。

2. 发明授权

US07426377B2 Sigma delta (ΣΔ) transmitter circuits and transceiver using the same 失效
标题翻译： Sigma delta（SigmaDelta）发射机电路和收发器使用相同
公开(公告)号：US07426377B2
公开(公告)日：2008-09-16
申请号：US11207003
申请日：2005-08-19
申请人： Satoshi Tanaka , Kazuyuki Hori , Manabu Kawabe , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Satoshi Tanaka , Kazuyuki Hori , Manabu Kawabe , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H04B1/06
CPC分类号： H04B1/406 , H04B1/0003
摘要： A ΣΔ transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90°, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.
摘要翻译：即使在多个频带中工作的情况下，也可以将环路滤波器LF，电荷泵电流和其他因素设定为相同条件的SigmaDelta发送器，因此允许减少部件的数量，并且同时启用要提供用于接收的本地信号的相位之间的角度接近正好90°，这是确保对元件间变化的鲁棒性并因此适合于大规模集成的特征。将VCO的振荡频率设定为发送频率的偶数倍，经由分频器生成发送信号。根据调制信号的幅度分量来改变增益的装置被添加到其输入是来自VCO的信号的放大器，并且由此使得涉及幅度调制（例如EDGE）的调制信号的传输成为可能。

3. 发明授权

US07301405B2 Phase locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US07301405B2
公开(公告)日：2007-11-27
申请号：US11202266
申请日：2005-08-12
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

4. 发明申请

US20060049878A1 Phase locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US20060049878A1
公开(公告)日：2006-03-09
申请号：US11202266
申请日：2005-08-12
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

5. 发明授权

US07800452B2 Phase locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US07800452B2
公开(公告)日：2010-09-21
申请号：US11976408
申请日：2007-10-24
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation.This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

6. 发明申请

US20080061890A1 Phase locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US20080061890A1
公开(公告)日：2008-03-13
申请号：US11976408
申请日：2007-10-24
申请人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
发明人： Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03C3/0925 , H03C3/0941 , H03C3/0991 , H03L7/1974 , H03L7/1976
摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
摘要翻译：本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

7. 发明授权

US07683723B2 Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems 有权
标题翻译：锁相环电路，偏移PLL发射机，射频集成电路和手机系统
公开(公告)号：US07683723B2
公开(公告)日：2010-03-23
申请号：US11865729
申请日：2007-10-02
申请人： Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
发明人： Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
IPC分类号： H03L7/07 , H03L7/085
CPC分类号： H03L7/0895 , H03C3/0933 , H03C3/0966 , H03C3/0983 , H03C3/0991 , H03L7/0898 , H03L7/107 , H03L7/185
摘要： A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
摘要翻译：配有环路增益检测电路的PLL电路，可以抑制环路增益的变化。当检测到环路增益时，首先改变相位检测器的第二输入（IN-2）的输入信号的频率，并且通过电压锁定振荡器的输出来检测对应于该变化的响应。通过将电压锁定振荡器的输出与计数器连接并将计数器的输出与积分器连接来进行检测。通过对电荷泵电流值的检测结果执行反馈来优化锁相环特性。

8. 发明授权

US07352250B2 Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems 有权
标题翻译：锁相环电路，偏移PLL发射机，射频集成电路和手机系统
公开(公告)号：US07352250B2
公开(公告)日：2008-04-01
申请号：US11341615
申请日：2006-01-30
申请人： Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
发明人： Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
IPC分类号： H03L7/07 , H03L7/085
CPC分类号： H03L7/0895 , H03C3/0933 , H03C3/0966 , H03C3/0983 , H03C3/0991 , H03L7/0898 , H03L7/107 , H03L7/185
摘要： A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
摘要翻译：配有环路增益检测电路的PLL电路，可以抑制环路增益的变化。当检测到环路增益时，首先改变到相位检测器的第二输入（IN-2）的输入信号的频率，并且通过电压锁定振荡器的输出来检测对应于该变化的响应。通过将电压锁定振荡器的输出与计数器连接并将计数器的输出与积分器连接来进行检测。通过对电荷泵电流值的检测结果执行反馈来优化锁相环特性。

9. 发明申请

US20080030281A1 PHASE LOCKED LOOP CIRCUITS, OFFSET PLL TRANSMITTERS, RADIO FREQUENCY INTEGRATED CIRCUITS AND MOBILE PHONE SYSTEMS 有权
标题翻译：相位锁定环路，偏移PLL发射器，无线电频率集成电路和移动电话系统
公开(公告)号：US20080030281A1
公开(公告)日：2008-02-07
申请号：US11865729
申请日：2007-10-02
申请人： Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
发明人： Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
IPC分类号： H03L7/085 , H03L7/07
CPC分类号： H03L7/0895 , H03C3/0933 , H03C3/0966 , H03C3/0983 , H03C3/0991 , H03L7/0898 , H03L7/107 , H03L7/185
摘要： A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
摘要翻译：配有环路增益检测电路的PLL电路，可以抑制环路增益的变化。当检测到环路增益时，首先改变到相位检测器的第二输入（IN-2）的输入信号的频率，并且通过电压锁定振荡器的输出来检测对应于该变化的响应。通过将电压锁定振荡器的输出与计数器连接并将计数器的输出与积分器连接来进行检测。通过对电荷泵电流值的检测结果执行反馈来优化锁相环特性。

10. 发明申请

US20060220750A1 Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems 有权
标题翻译：锁相环电路，偏移PLL发射机，射频集成电路和手机系统
公开(公告)号：US20060220750A1
公开(公告)日：2006-10-05
申请号：US11341615
申请日：2006-01-30
申请人： Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
发明人： Yukinori Akamine , Manabu Kawabe , Satoshi Tanaka , Yasuo Shima , Ryoichi Takano
IPC分类号： H03L7/00
CPC分类号： H03L7/0895 , H03C3/0933 , H03C3/0966 , H03C3/0983 , H03C3/0991 , H03L7/0898 , H03L7/107 , H03L7/185
摘要： A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
摘要翻译：配有环路增益检测电路的PLL电路，可以抑制环路增益的变化。当检测到环路增益时，首先改变到相位检测器的第二输入（IN-2）的输入信号的频率，并且通过电压锁定振荡器的输出来检测对应于该变化的响应。通过将电压锁定振荡器的输出与计数器连接并将计数器的输出与积分器连接来进行检测。通过对电荷泵电流值的检测结果执行反馈来优化锁相环特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式