专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07246126B2 Communications system for retrieving instruction files from a server 有权
标题翻译：用于从服务器检索指令文件的通信系统
公开(公告)号：US07246126B2
公开(公告)日：2007-07-17
申请号：US10046172
申请日：2002-01-16
申请人： Satoshi Inami , Takako Hirose , Masashige Mizuyama , Atsunobu Kato , Munehito Matsuda , Hidehiko Shin , Hiromi Wada
发明人： Satoshi Inami , Takako Hirose , Masashige Mizuyama , Atsunobu Kato , Munehito Matsuda , Hidehiko Shin , Hiromi Wada
IPC分类号： G06F7/00 , G06F15/173 , G06F17/30
CPC分类号： H04L67/34 , A63F13/12 , A63F13/35 , A63F2300/407 , A63F2300/552 , H04L29/06
摘要： A terminal-side communications control unit makes a request to a server for retrieving an instruction file that describes an instruction for transmitting transmission data. The server transmits the instruction file in response to the request for retrieving the instruction file. On receiving the instruction file, the terminal-side communications control unit causes an application executing unit to execute an application, and also forwards the instruction file to a transmission data generating unit. On receiving the instruction file, the transmission data generating part refers to the instruction file to generate, from generated data stored in a generated data storage unit, transmission data to be transmitted to the server.
摘要翻译：终端侧通信控制单元向服务器请求检索描述用于发送传输数据的指令的指令文件。服务器响应于检索指令文件的请求而发送指令文件。在接收到指令文件时，终端侧通信控制单元使应用执行单元执行应用，并且将指令文件转发到发送数据生成单元。发送数据生成部在接收到指示文件时，参照指示文件，从存储在生成数据存储部中的生成数据生成要发送给服务器的发送数据。

2. 发明授权

US06920481B2 Communications terminal 有权
标题翻译：通讯终端
公开(公告)号：US06920481B2
公开(公告)日：2005-07-19
申请号：US10046184
申请日：2002-01-16
申请人： Satoshi Inami , Masashige Mizuyama , Atsunobu Kato
发明人： Satoshi Inami , Masashige Mizuyama , Atsunobu Kato
IPC分类号： G06F21/31 , G06F15/16
CPC分类号： G06F21/31
摘要： In a communications terminal 3, a CPU 32 retrieves start-up data 112 from a server 1 using a Web browser 311, which is stored in a storage device 31. The CPU 32 performs data authentication with respect to authentication type data 1123 included in the start-up data 112. Then, when the authentication is succeeded, the CPU 32 follows the authentication type data 1123 so as to determine which authentication mode is to be used for authenticating the application data. In this manner, the authentication mode for authenticating the application data can be easily changed.
摘要翻译：在通信终端3中，CPU32使用存储在存储装置31中的Web浏览器311从服务器1检索启动数据112.CPU32对包含在存储装置31中的认证类型数据1123进行数据认证启动数据112.然后，当认证成功时，CPU 32遵循认证类型数据1123，以便确定哪个认证模式将用于认证应用数据。以这种方式，可以容易地改变用于认证应用数据的认证模式。

3. 发明授权

US08489862B2 Multiprocessor control apparatus for controlling a plurality of processors sharing a memory and an internal bus and multiprocessor control method and multiprocessor control circuit for performing the same 有权
标题翻译：用于控制共享存储器的多个处理器和内部总线的多处理器控制装置和多处理器控制方法以及用于执行该处理器的多处理器控制电路
公开(公告)号：US08489862B2
公开(公告)日：2013-07-16
申请号：US12663932
申请日：2008-06-05
申请人： Masahiko Saito , Masashige Mizuyama
发明人： Masahiko Saito , Masashige Mizuyama
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F9/45533 , G06F9/52 , G06F12/0831 , G06F12/0864 , G06F2212/1028 , Y02D10/122 , Y02D10/13 , Y02D10/171 , Y02D10/24 , Y02D10/26 , Y02D10/28 , Y02D50/20
摘要： An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which executes a second instruction code, a hypervisor (130) which converts the second instruction code into an instruction code executable by the first processor (141); and a power control circuit (170) which controls the operation of at least one of the first processor (141) and the second processor (151). When the operation of the second processor (151) is suppressed by the power control circuit (170), the hypervisor (130) converts the second instruction code into the instruction code executable by the first processor (141), and the first processor (141) executes the converted instruction code.
摘要翻译：本发明的一个目的是减少由多个处理器中暂时激活需要大功率消耗的处理器所产生的电力消耗。多处理器系统（1）包括：执行第一指令代码的第一处理器（141）执行第二指令代码的第二处理器（151），将第二指令代码转换成可由第一处理器（141）执行的指令代码的管理程序（130）; 以及控制第一处理器（141）和第二处理器（151）中的至少一个的操作的功率控制电路（170）。当由功率控制电路（170）抑制第二处理器（151）的操作时，管理程序（130）将第二指令代码转换为可由第一处理器（141）执行的指令代码，第一处理器（141））执行转换的指令代码。

4. 发明申请

US20060161922A1 Task scheduling apparatus, method, program, storage medium and transmission medium for prioritized signal handler scheduling 有权
标题翻译：任务调度装置，方法，程序，存储介质和优先级信号处理程序调度的传输介质
公开(公告)号：US20060161922A1
公开(公告)日：2006-07-20
申请号：US10563436
申请日：2004-12-24
申请人： Katsushige Amano , Masashige Mizuyama
发明人： Katsushige Amano , Masashige Mizuyama
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F9/4881
摘要： Each task #1, #2 registers signal handlers belonging thereto in a signal-handler table 112 through a handler registering section 111 in an OS 100, and registers itself and the priority thereof in a task/handler priority table 101 through a task registering section. When a signal is generated, a signal notifying section 131 specifies a signal handler corresponding to the signal and the priority thereof by referring to the signal-handler table 112, and a task/handler selecting section 141 selects a task or signal handler having a highest priority in the task/handler priority table 101. A task executing section 150 executes the selected task and a signal-handler executing section 151 executes the selected signal handler.
摘要翻译：每个任务＃1，＃2通过OS 100中的处理机登记部分111在信号处理器表112中登记属于其的信号处理程序，并通过任务登记部分将其自身及其优先级登记在任务/处理程序优先级表101中。当产生信号时，信号通知部分131通过参考信号处理器表112指定与信号及其优先级相对应的信号处理器，并且任务/处理器选择部分141选择具有最高值的任务或信号处理器任务/处理程序优先级表101中的优先级。任务执行部分150执行所选择的任务，信号处理程序执行部分151执行所选择的信号处理程序。

5. 发明申请

US20060195847A1 Task scheduling device, method, program, recording medium, and transmission medium for priority-driven periodic process scheduling 审中-公开
标题翻译：任务调度设备，方法，程序，记录介质和用于优先级驱动的周期性过程调度的传输介质
公开(公告)号：US20060195847A1
公开(公告)日：2006-08-31
申请号：US10563060
申请日：2004-12-03
申请人： Katsushige Amano , Masashige Mizuyama
发明人： Katsushige Amano , Masashige Mizuyama
IPC分类号： G06F9/46
CPC分类号： G06F9/4887
摘要： A high priority setter 102 writes the first priority (high priority) of a specific task #1 recorded in a specific task table 110 every time interval T, as the priority of the task #1 in a task priority table 111. Thereafter, when a time duration TH shorter than the time interval T elapsed, a low priority setter 103 writes the second priority (low priority) of the specific task #1 recorded in the specific task table 110, as the priority of the task #1 in the task priority table 111. The second priority is set lower than the first priority. A task selector 101 selects a task whose priority is set the highest among the tasks 10 recorded in the task priority table 111, as a specific task to be executed. Thus, the processing of the specific task #1 is securely executed during the time duration TH every time interval T, and the execution of the specific task #1 is allowed to continue if it is judged that there is no other task to be executed during the rest of the time interval T other than the time duration TH, by setting the first priority sufficiently high.
摘要翻译：高优先级设置器102将每个时间间隔T中记录在特定任务表110中的特定任务＃1的第一优先级（高优先级）写入任务优先级表111中的任务＃1的优先级。此后，当经过比时间间隔T短的持续时间TH时，低优先级设定器103将记录在特定任务表110中的特定任务＃1的第二优先级（低优先级）写入任务＃1的优先级在任务优先级表111中。第二个优先级设置为低于第一优先级。任务选择器101将记录在任务优先表111中的任务10中的优先级设定为最高的任务作为要执行的特定任务。因此，特定任务＃1的处理在每个时间间隔T的持续时间TH期间被安全地执行，并且如果判断为不执行其他任务，则允许特定任务＃1的执行继续执行剩余的时间间隔T，除了持续时间TH之外，通过将第一优先级设置得足够高。

6. 发明申请

US20050144408A1 Memory protection unit, memory protection method, and computer-readable record medium in which memory protection program is recorded 审中-公开
标题翻译：存储器保护单元，存储器保护方法和记录存储器保护程序的计算机可读记录介质
公开(公告)号：US20050144408A1
公开(公告)日：2005-06-30
申请号：US11020527
申请日：2004-12-27
申请人： Kenji Ejima , Masashige Mizuyama
发明人： Kenji Ejima , Masashige Mizuyama
IPC分类号： G06F12/14 , G06F21/00
CPC分类号： G06F21/52
摘要： A memory protection unit, a memory protection method and a computer-readable record medium in which a memory protection program is recorded is provided which are capable of preventing a memory from being improperly rewritten by a malfunction in a subroutine. This memory protection unit includes: a memory which has at least one memory area that is used by at least one subroutine, and in which a writing attribute that shows a writing permission or a writing prohibition can be set for every memory area; a subroutine choice section which chooses a subroutine that executes a processing request; a memory-area specification section which specifies a memory area that is used by the subroutine; and a subroutine calling section which sets, to the writing permission, the writing attribute of the specified memory area, calls the chosen subroutine, and sets, to the writing prohibition, the writing attribute of the memory area after completing the execution of the subroutine.
摘要翻译：提供了一种存储器保护单元，存储器保护方法和其中记录存储器保护程序的计算机可读记录介质，其能够防止存储器由于子程序中的故障而被不正确地重写。该存储器保护单元包括：存储器，其具有由至少一个子程序使用的至少一个存储区域，并且其中可以为每个存储区域设置显示写入许可或写入禁止的写入属性; 子程序选择部分，其选择执行处理请求的子程序; 指定由子程序使用的存储区域的存储器区域规范部分; 以及子程序调用部分，其对写入许可设置指定存储区域的写入属性，调用所选择的子程序，并且在完成子程序的执行之后将写入禁止设置为存储区域的写入属性。

7. 发明申请

US20080307248A1 Cpu Clock Control Device, Cpu Clock Control Method, Cpu Clock Control Program, Recording Medium, and Transmission Medium 审中-公开
标题翻译： Cpu时钟控制装置，Cpu时钟控制方式，Cpu时钟控制程序，记录介质和传输介质
公开(公告)号：US20080307248A1
公开(公告)日：2008-12-11
申请号：US10583657
申请日：2005-04-20
申请人： Katsushige Amano , Masashige Mizuyama
发明人： Katsushige Amano , Masashige Mizuyama
IPC分类号： G06F1/08 , G06F9/46 , G06F13/24
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , Y02D10/126
摘要： A program execution time determining portion determines an execution start time and a processing volume per unit time of a program in such a manner that a processing volume necessary to execute the program is made equal to the extent that registered request for the execution time and allowable range are met. It is thus possible to determine the execution time of the program in such a manner that a necessary processing volume is made as equal as possible within the allowable range of the request for the execution time of the program, which enables clock control that suppresses a variation of the operating frequency of the CPU. Power consumption of the CPU can be thus reduced.
摘要翻译：程序执行时间确定部分以使得执行程序所需的处理量等于执行时间和可允许范围的注册请求的程度来确定程序的每单位时间的执行开始时间和处理量得到满足因此，可以以使程序的执行时间的请求的允许范围内尽可能地使必要的处理量相等的方式来确定程序的执行时间，这使得能够抑制变化的时钟控制的CPU的工作频率。因此可以减少CPU的功耗。

8. 发明授权

US07346791B2 Method for controlling a clock frequency of an information processor in accordance with the detection of a start and a end of a specific processing section 有权
标题翻译：根据特定处理部分的开始和结束的检测来控制信息处理器的时钟频率的方法
公开(公告)号：US07346791B2
公开(公告)日：2008-03-18
申请号：US10808438
申请日：2004-03-25
申请人： Kazuomi Kato , Masashige Mizuyama
发明人： Kazuomi Kato , Masashige Mizuyama
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： A clock controller controls a clock generated by a clock generator to determine a clock frequency. A computing device executes software obtained from a storage in accordance with the clock supplied via the clock controller. An exclusive processing section detector detects the start and end of an exclusive processing section which is a section during which an exclusive processing is executed. A clock control judging device commands the clock controller to decrease the clock frequency if the exclusive processing section detector has detected the start of a specific processing section, while commanding the clock controller to decrease the clock frequency if the exclusive processing section detector has detected the end of the specific processing section.
摘要翻译：时钟控制器控制由时钟发生器产生的时钟来确定时钟频率。计算装置根据经由时钟控制器提供的时钟，执行从存储器获得的软件。独占处理部检测器检测作为执行排他处理的部分的排他处理部的开始和结束。如果专用处理部检测器检测到特定处理部分的开始，则时钟控制判断装置命令时钟控制器降低时钟频率，同时如果专用处理部分检测器已经检测到结束，则命令时钟控制器降低时钟频率的具体处理部。

9. 发明授权

US07831973B2 Task scheduling apparatus, task scheduling method, task scheduling program, storage medium and transmission medium 有权
标题翻译：任务调度设备，任务调度方式，任务调度程序，存储介质和传输介质
公开(公告)号：US07831973B2
公开(公告)日：2010-11-09
申请号：US10563436
申请日：2004-12-24
申请人： Katsushige Amano , Masashige Mizuyama
发明人： Katsushige Amano , Masashige Mizuyama
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F9/4881
摘要： Each task #1, #2 registers signal handlers belonging thereto in a signal-handler table through a handler registering section in an OS, and registers itself and the priority thereof in a task/handler priority table through a task registering section. When a signal is generated, a signal notifying section specifies a signal handler corresponding to the signal and the priority thereof by referring to the signal-handler table, and a task/handler selecting section selects a task or signal handler having a highest priority in the task/handler priority table. A task executing section executes the selected task and a signal-handler executing section executes the selected signal handler.
摘要翻译：每个任务＃1，＃2通过OS中的处理器注册部分在信号处理器表中登记属于其的信号处理程序，并通过任务登记部分将其自身及其优先级登记在任务/处理程序优先级表中。当产生信号时，信号通知部分通过参考信号处理程序表来指定与信号及其优先级对应的信号处理器，并且任务/处理程序选择部分选择具有最高优先级的任务或信号处理程序 task / handler优先级表。任务执行部分执行所选择的任务，并且信号处理程序执行部分执行所选择的信号处理程序。

10. 发明申请

US20100185833A1 MULTIPROCESSOR CONTROL APPARATUS, MULTIPROCESSOR CONTROL METHOD, AND MULTIPROCESSOR CONTROL CIRCUIT 有权
标题翻译：多处理器控制装置，多处理器控制方法和多处理器控制电路
公开(公告)号：US20100185833A1
公开(公告)日：2010-07-22
申请号：US12663932
申请日：2008-06-05
申请人： Masahiko Saito , Masashige Mizuyama
发明人： Masahiko Saito , Masashige Mizuyama
IPC分类号： G06F9/318 , G06F1/32 , G06F12/08
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F9/45533 , G06F9/52 , G06F12/0831 , G06F12/0864 , G06F2212/1028 , Y02D10/122 , Y02D10/13 , Y02D10/171 , Y02D10/24 , Y02D10/26 , Y02D10/28 , Y02D50/20
摘要： An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which executes a second instruction code, a hypervisor (130) which converts the second instruction code into an instruction code executable by the first processor (141); and a power control circuit (170) which controls the operation of at least one of the first processor (141) and the second processor (151). When the operation of the second processor (151) is suppressed by the power control circuit (170), the hypervisor (130) converts the second instruction code into the instruction code executable by the first processor (141), and the first processor (141) executes the converted instruction code.
摘要翻译：本发明的一个目的是减少由多个处理器中暂时激活需要大功率消耗的处理器所产生的电力消耗。多处理器系统（1）包括：执行第一指令代码的第一处理器（141）执行第二指令代码的第二处理器（151），将第二指令代码转换成可由第一处理器（141）执行的指令代码的管理程序（130）; 以及控制第一处理器（141）和第二处理器（151）中的至少一个的操作的功率控制电路（170）。当由功率控制电路（170）抑制第二处理器（151）的操作时，管理程序（130）将第二指令代码转换为可由第一处理器（141）执行的指令代码，第一处理器（141））执行转换的指令代码。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式