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1. 发明授权

US08236708B2 Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor 失效
标题翻译：使用双（二乙基氨基）硅烷（C 8 H 22 N 2 Si）作为硅前体的减少图案负载
公开(公告)号：US08236708B2
公开(公告)日：2012-08-07
申请号：US12855877
申请日：2010-08-13
申请人： Sasha Kweskin , Paul Edward Gee , Shankar Venkataraman , Kedar Sapre
发明人： Sasha Kweskin , Paul Edward Gee , Shankar Venkataraman , Kedar Sapre
IPC分类号： H01L21/316 , C23C16/40
CPC分类号： H01L21/02219 , C23C16/401 , H01L21/02164 , H01L21/02271
摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
摘要翻译：本公开的方面涉及在图案化衬底上沉积电介质层的方法。在实施方案中，通过将BIS（二乙胺）硅烷（BDEAS），臭氧和分子氧流入处理室来沉积电介质层，使得跨越图案化的衬底表面实现相对均匀的电介质生长速率。根据实施例生长的电介质层的沉积可以减少对图案密度的依赖性，同时仍然适用于非牺牲应用。

2. 发明授权

US07994019B1 Silicon-ozone CVD with reduced pattern loading using incubation period deposition 失效
标题翻译：硅 - 臭氧CVD，使用潜伏期沉积减少图案负载
公开(公告)号：US07994019B1
公开(公告)日：2011-08-09
申请号：US12891149
申请日：2010-09-27
申请人： Sasha Kweskin , Paul Edward Gee , Shankar Venkataraman , Kedar Sapre
发明人： Sasha Kweskin , Paul Edward Gee , Shankar Venkataraman , Kedar Sapre
IPC分类号： H01L21/00
CPC分类号： H01L21/02164 , C23C16/401 , C23C16/45523 , H01L21/0228
摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.
摘要翻译：本公开的方面涉及在图案化衬底上沉积保形氧化硅层的方法。在实施例中，通过将含硅前体和臭氧流入处理室来沉积电介质层，使得跨越具有异质材料的图案化衬底表面和/或异质图案密度分布实现相对均匀的介电生长速率。根据实施例生长的电介质层的沉积可以降低对下层材料和图案密度的依赖性，同时仍然适用于非牺牲应用。依靠图案密度的减少是通过在潜伏期结束时终止沉积来实现的。多个沉积循环可以串联进行，因为在沉积停顿之后潜伏期的有益特性可以重复。

3. 发明申请

US20110223774A1 REDUCED PATTERN LOADING USING BIS(DIETHYLAMINO)SILANE (C8H22N2Si) AS SILICON PRECURSOR 失效
标题翻译：使用BIS（二乙基氨基）硅烷（C8H22N2Si）作为硅前体的减少图案加载
公开(公告)号：US20110223774A1
公开(公告)日：2011-09-15
申请号：US12855877
申请日：2010-08-13
申请人： Sasha Kweskin , Paul Edward Gee , Shankar Venkataraman , Kedar Sapre
发明人： Sasha Kweskin , Paul Edward Gee , Shankar Venkataraman , Kedar Sapre
IPC分类号： H01L21/316
CPC分类号： H01L21/02219 , C23C16/401 , H01L21/02164 , H01L21/02271
摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
摘要翻译：本公开的方面涉及在图案化衬底上沉积电介质层的方法。在实施方案中，通过将BIS（二乙胺）硅烷（BDEAS），臭氧和分子氧流入处理室来沉积电介质层，使得跨越图案化的衬底表面实现相对均匀的电介质生长速率。根据实施例生长的电介质层的沉积可以减少对图案密度的依赖性，同时仍然适用于非牺牲应用。

4. 发明授权

US08476142B2 Preferential dielectric gapfill 有权
标题翻译：优选电介质填隙
公开(公告)号：US08476142B2
公开(公告)日：2013-07-02
申请号：US13052238
申请日：2011-03-21
申请人： Sasha Kweskin , Hiroshi Hamana , Paul Edward Gee , Shankar Venkataraman , Kadar Sapre
发明人： Sasha Kweskin , Hiroshi Hamana , Paul Edward Gee , Shankar Venkataraman , Kadar Sapre
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/67017
摘要： Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.
摘要翻译：本公开的方面涉及优先用氧化硅填充窄沟槽而不完全填充较宽的沟槽和/或开放区域的方法。在实施例中，通过使含硅前体和臭氧流入处理室来沉积电介质层，使得氧化硅层的相对致密的第一部分，随后是氧化硅层的更多孔（并且更快蚀刻）的第二部分。狭窄的沟槽填充有致密的材料，而开放区域被一层致密材料和更多孔的材料覆盖。在较宽的沟槽中的电介质材料可以在这一点用湿法蚀刻去除，而狭窄沟槽中的致密材料被保留。

5. 发明申请

US20110250731A1 PREFERENTIAL DIELECTRIC GAPFILL 有权
标题翻译：优选电介质
公开(公告)号：US20110250731A1
公开(公告)日：2011-10-13
申请号：US13052238
申请日：2011-03-21
申请人： Sasha Kweskin , Hiroshi Hamana , Paul Edward Gee , Shankar Venkataraman , Kadar Sapre
发明人： Sasha Kweskin , Hiroshi Hamana , Paul Edward Gee , Shankar Venkataraman , Kadar Sapre
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/67017
摘要： Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.
摘要翻译：本公开的方面涉及优先用氧化硅填充窄沟槽而不完全填充较宽的沟槽和/或开放区域的方法。在实施例中，通过使含硅前体和臭氧流入处理室来沉积电介质层，使得氧化硅层的相对致密的第一部分，随后是氧化硅层的更多孔（并且更快蚀刻）的第二部分。狭窄的沟槽填充有致密的材料，而开放区域被一层致密材料和更多孔的材料覆盖。在较宽的沟槽中的电介质材料可以在这一点用湿法蚀刻去除，而狭窄沟槽中的致密材料被保留。

6. 发明授权

US08012887B2 Precursor addition to silicon oxide CVD for improved low temperature gapfill 失效
标题翻译：添加氧化硅CVD用于改善低温缝隙填料的前体
公开(公告)号：US08012887B2
公开(公告)日：2011-09-06
申请号：US12489234
申请日：2009-06-22
申请人： Shankar Venkataraman , Hiroshi Hamana , Manuel A. Hernandez , Nitin K. Ingle , Paul Edward Gee
发明人： Shankar Venkataraman , Hiroshi Hamana , Manuel A. Hernandez , Nitin K. Ingle , Paul Edward Gee
IPC分类号： H01L21/31 , C23C16/00
CPC分类号： H01L21/31612 , C23C16/401 , H01L21/02164 , H01L21/02211 , H01L21/02216 , H01L21/02222 , H01L21/02271 , H01L21/76224
摘要： Methods of depositing silicon oxide layers on substrates involve flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that a uniform silicon oxide growth rate is achieved across the substrate surface. The surface of silicon oxide layers grown according to embodiments may have a reduced roughness when grown with the additive precursor. In other aspects of the disclosure, silicon oxide layers are deposited on a patterned substrate with trenches on the surface by flowing a silicon-containing precursor, an oxidizing gas, water and an additive precursor into a processing chamber such that the trenches are filled with a reduced quantity and/or size of voids within the silicon oxide filler material.
摘要翻译：在衬底上沉积氧化硅层的方法包括使含硅前体，氧化气体，水和添加剂前体流入处理室，使得在衬底表面上实现均匀的氧化硅生长速率。根据实施例生长的氧化硅层的表面可以在与添加剂前体一起生长时具有减小的粗糙度。在本公开的其他方面中，通过使含硅前体，氧化气体，水和添加剂前体流入处理室，将硅氧化物层沉积在具有表面上的沟槽的图案化衬底上，使得沟槽填充有氧化硅填充材料内的空隙的数量和/或尺寸减小。

7. 发明申请

US20120225565A1 REDUCED PATTERN LOADING USING SILICON OXIDE MULTI-LAYERS 有权
标题翻译：使用硅氧化物多层的减少图案加载
公开(公告)号：US20120225565A1
公开(公告)日：2012-09-06
申请号：US13251621
申请日：2011-10-03
申请人： Sidharth Bhatia , Paul Edward Gee , Shankar Venkataraman
发明人： Sidharth Bhatia , Paul Edward Gee , Shankar Venkataraman
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , C23C16/402 , C23C16/452 , C23C16/45523 , H01L21/02164 , H01L21/02219 , H01L21/02271 , H01L21/0234 , H01L21/28556
摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
摘要翻译：本公开的方面涉及在图案化衬底上沉积适形氧化硅多层的方法。共形氧化硅多层各自通过沉积多个子层形成。通过将BIS（二乙基氨基）硅烷（BDEAS）和含氧前体流入处理室来沉积子层，使得在图案化的衬底表面上实现相对均匀的介电生长速率。等离子体处理可以随后形成亚层，以进一步改善保形性并降低保形氧化硅多层膜的湿蚀刻速率。根据实施例生长的共形氧化硅多层的沉积对图案密度的依赖性降低，同时仍然适用于非牺牲应用。

8. 发明授权

US08716154B2 Reduced pattern loading using silicon oxide multi-layers 有权
标题翻译：使用氧化硅多层的减少图案加载
公开(公告)号：US08716154B2
公开(公告)日：2014-05-06
申请号：US13251621
申请日：2011-10-03
申请人： Sidharth Bhatia , Paul Edward Gee , Shankar Venkataraman
发明人： Sidharth Bhatia , Paul Edward Gee , Shankar Venkataraman
IPC分类号： H01L21/31 , H01L21/02
CPC分类号： H01L21/0228 , C23C16/402 , C23C16/452 , C23C16/45523 , H01L21/02164 , H01L21/02219 , H01L21/02271 , H01L21/0234 , H01L21/28556
摘要： Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
摘要翻译：本公开的方面涉及在图案化衬底上沉积适形氧化硅多层的方法。共形氧化硅多层各自通过沉积多个子层形成。通过将BIS（二乙基氨基）硅烷（BDEAS）和含氧前体流入处理室来沉积子层，使得在图案化的衬底表面上实现相对均匀的介电生长速率。等离子体处理可以随后形成亚层，以进一步改善保形性并降低保形氧化硅多层膜的湿蚀刻速率。根据实施例生长的共形氧化硅多层的沉积对图案密度的依赖性降低，同时仍然适用于非牺牲应用。

9. 发明申请

US20120094468A1 TWO SILICON-CONTAINING PRECURSORS FOR GAPFILL ENHANCING DIELECTRIC LINER 有权
标题翻译：两种含硅前驱物，用于增强电介质衬垫
公开(公告)号：US20120094468A1
公开(公告)日：2012-04-19
申请号：US13182671
申请日：2011-07-14
申请人： Sidharth Bhatia , Hiroshi Hamana , Paul Edward Gee , Shankar Venkataraman
发明人： Sidharth Bhatia , Hiroshi Hamana , Paul Edward Gee , Shankar Venkataraman
IPC分类号： H01L21/762 , B82Y40/00
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02216 , H01L21/02222 , H01L21/02271
摘要： Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.
摘要翻译：本公开的方面涉及在衬底上沉积氧化硅层的方法。在实施例中，通过将具有Si-O键的含硅前体，含氧前体和具有Si-C键和Si-N键的第二含硅前体流过，沉积氧化硅层，半导体处理室以形成保形衬里层。在衬里层完成时，通过将具有Si-O键的含硅前体，含氧前体流入半导体处理室来形成间隙填充层。保形衬垫层的存在提高了间隙填充层更平稳地生长，填充沟槽并且在氧化硅填料材料内产生减少量和/或尺寸的空隙的能力。

10. 发明授权

US08664127B2 Two silicon-containing precursors for gapfill enhancing dielectric liner 有权
标题翻译：两种含硅前体，用于填隙增强电介质衬垫
公开(公告)号：US08664127B2
公开(公告)日：2014-03-04
申请号：US13182671
申请日：2011-07-14
申请人： Sidharth Bhatia , Hiroshi Hamana , Paul Edward Gee , Shankar Venkataraman
发明人： Sidharth Bhatia , Hiroshi Hamana , Paul Edward Gee , Shankar Venkataraman
IPC分类号： H01L21/00
CPC分类号： H01L21/76224 , B82Y10/00 , H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02216 , H01L21/02222 , H01L21/02271
摘要： Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.
摘要翻译：本公开的方面涉及在衬底上沉积氧化硅层的方法。在实施例中，通过将具有Si-O键的含硅前体，含氧前体和具有Si-C键和Si-N键的第二含硅前体流过，沉积氧化硅层，半导体处理室以形成保形衬里层。在衬里层完成时，通过将具有Si-O键的含硅前体，含氧前体流入半导体处理室来形成间隙填充层。保形衬垫层的存在提高了间隙填充层更平稳地生长，填充沟槽并且在氧化硅填料材料内产生减少量和/或尺寸的空隙的能力。

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