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1. 发明授权

US09113033B2 Mobile video conferencing with digital annotation 有权
标题翻译：具有数字注释的移动视频会议
公开(公告)号：US09113033B2
公开(公告)日：2015-08-18
申请号：US13596464
申请日：2012-08-28
申请人： Sasa Junuzovic , Kori Inkpen Quinn , Anoop Gupta , Aaron Hoff , Gina Venolia , Andreas Nowatzyk , Hrvoje Benko , Gavin Jancke , John Tang
发明人： Sasa Junuzovic , Kori Inkpen Quinn , Anoop Gupta , Aaron Hoff , Gina Venolia , Andreas Nowatzyk , Hrvoje Benko , Gavin Jancke , John Tang
IPC分类号： H04N7/15 , G06Q10/10 , H04L12/18
CPC分类号： H04N7/15 , G06Q10/101 , H04L12/1822
摘要： A local user of a local mobile device is allowed to participate in a video conference session with a remote user of a remote mobile device. Live video can be shared between and collaboratively digitally annotated by the local and remote users. An application can also be shared between and collaboratively digitally annotated by the local and remote users. A digital object can also be shared between and collaboratively digitally annotated by the local and remote users.
摘要翻译：允许本地移动设备的本地用户参与与远程移动设备的远程用户的视频会议会话。实时视频可以由本地和远程用户之间共享和协作地数字注释。应用程序也可以由本地和远程用户之间共享和协作地数字注释。数字对象也可以由本地和远程用户之间共享和协作地数字注释。

2. 发明申请

US20140063174A1 MOBILE VIDEO CONFERENCING WITH DIGITAL ANNOTATION 有权
标题翻译：移动视频会议与数字宣传
公开(公告)号：US20140063174A1
公开(公告)日：2014-03-06
申请号：US13596464
申请日：2012-08-28
申请人： Sasa Junuzovic , Kori Inkpen Quinn , Anoop Gupta , Aaron Hoff , Gina Venolia , Andreas Nowatzyk , Hrvoje Benko , Gavin Jancke , John Tang
发明人： Sasa Junuzovic , Kori Inkpen Quinn , Anoop Gupta , Aaron Hoff , Gina Venolia , Andreas Nowatzyk , Hrvoje Benko , Gavin Jancke , John Tang
IPC分类号： H04N7/15
CPC分类号： H04N7/15 , G06Q10/101 , H04L12/1822
摘要： A local user of a local mobile device is allowed to participate in a video conference session with a remote user of a remote mobile device. Live video can be shared between and collaboratively digitally annotated by the local and remote users. An application can also be shared between and collaboratively digitally annotated by the local and remote users. A digital object can also be shared between and collaboratively digitally annotated by the local and remote users.
摘要翻译：允许本地移动设备的本地用户参与与远程移动设备的远程用户的视频会议会话。实时视频可以由本地和远程用户之间共享和协作地数字注释。应用程序也可以由本地和远程用户之间共享和协作地数字注释。数字对象也可以由本地和远程用户之间共享和协作地数字注释。

3. 发明授权

US07123211B2 Surround-vision display system 有权
标题翻译：环绕显示系统
公开(公告)号：US07123211B2
公开(公告)日：2006-10-17
申请号：US10633041
申请日：2003-07-31
申请人： Andreas Nowatzyk
发明人： Andreas Nowatzyk
IPC分类号： G09G5/00
CPC分类号： G09G3/005 , G03B25/02 , G09G3/2014 , G09G3/32
摘要： A surround-vision display system with a very high visual dynamic range is made possible by distributing a limited number of LED's on the inside of a drum and then spinning that drum around a user. The pixel information for each horizontal position in space is sent to each corresponding LED it visits that position. The LED's are arranged in a grid on a panel tile, and the panel tile is tilted slightly, e.g., at 1.1-degrees. The result is each panel tile presents a continuous vertical stripe in the picture frame as all its LED's are swept by in the drum motion. Several panel tiles stacked vertically inside the drum all contribute to the whole height of the picture frame, e.g., several feet. The entire inside circumference of the drum is populated with the LED panel tiles to keep frame refresh rates up to avoid flicker while keeping drum rotation speeds down to reasonable levels. Thus even though the LED's and drum are moving, the image projected appears to be relatively stationary.
摘要翻译：通过将有限数量的LED分配在鼓的内侧，然后将该鼓旋转到用户周围，可以实现具有非常高的视觉动态范围的环视显示系统。空间中每个水平位置的像素信息被发送到它访问该位置的每个对应的LED。 LED被布置在面板上的格子中，并且面板瓦稍微倾斜，例如以1.1度倾斜。结果是每个面板瓦片在图像帧中呈现连续的垂直条纹，因为其所有的LED被滚筒运动扫过。在滚筒内垂直堆叠的几个面板瓦片都有助于相框的整个高度，例如几英尺。滚筒的整个内圆周都装有LED面板瓦片，以保持框架刷新率，以避免闪烁，同时保持滚筒旋转速度降到合理的水平。因此，即使LED和鼓正在移动，投影的图像似乎相对静止。

4. 发明授权

US06925537B2 Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants 有权
标题翻译：多处理器高速缓存一致性系统和方法，其中处理器节点和输入/输出节点是相等的参与者
公开(公告)号：US06925537B2
公开(公告)日：2005-08-02
申请号：US10698130
申请日：2003-10-31
申请人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Mosur K. Ravishankar , Robert J. Stets, Jr.
发明人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Mosur K. Ravishankar , Robert J. Stets, Jr.
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0817 , G06F2212/621
摘要： A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
摘要翻译：计算机系统具有多个处理器节点和多个输入/输出节点。每个处理器节点包括多个处理器核心，到本地存储器系统的接口和实现预定义高速缓存一致性协议的协议引擎。每个处理器核心具有用于缓存存储器信息线的相关联的存储器缓存。每个输入/输出节点不包括处理器内核，用于与输入/输出总线或输入/输出设备进行接口的输入/输出接口，用于缓存存储器信息线的存储器缓存和到本地存储器子系统的接口。每个处理器节点和输入/输出节点的本地存储器子系统存储多个存储器信息线。每个处理器节点和输入/输出节点的协议引擎实现相同的预定义缓存一致性协议。

5. 发明授权

US06751720B2 Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy 失效
标题翻译：用于检测和解析两级缓存层次结构中的虚拟地址同义词的方法和系统
公开(公告)号：US06751720B2
公开(公告)日：2004-06-15
申请号：US10042054
申请日：2002-01-07
申请人： Luiz André Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Robert J. Stets, Jr. , Mosur Kumaraswamy Ravishankar
发明人： Luiz André Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Robert J. Stets, Jr. , Mosur Kumaraswamy Ravishankar
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.
摘要翻译：二级缓存系统中的L1缓存同义词通过L2缓存中的逻辑进行检测和解析。 L1缓存标签和状态（“Dtags”）的重复副本被保留在L2高速缓存中。在L1高速缓存中出现未命中之后，搜索对应于L1高速缓存中所有可能的同义词位置的二级高速缓存中的Dtags同义词。如果发现同义词，则L2缓存通知L1缓存，其中可以在L1缓存中找到所请求的高速缓存行。然后，L1高速缓存从发现同义词的位置复制缓存行到发生未命中的位置，并且使原始位置的高速缓存行无效。更新二级缓存中的Dtags以反映L1缓存中所做的更改。

6. 发明授权

US06725343B2 System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system 有权
标题翻译：用于在多处理器系统中生成高速缓存一致目录条目和纠错码的系统和方法
公开(公告)号：US06725343B2
公开(公告)日：2004-04-20
申请号：US09972477
申请日：2001-10-05
申请人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
发明人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F11/1064 , G06F11/1666 , G06F2212/2542
摘要： Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory. When the cache memory system of the home node stores an exclusive copy of the particular memory line, the logic responds to the request by sending the copy of the particular memory line retrieved from the cache memory system and a predefined null directory entry value, and thus does not retrieve the memory line and its directory entry from the main memory of the home node.
摘要翻译：多处理器计算机系统的每个节点包括主存储器，高速缓冲存储器系统和逻辑。主存储器存储数据的存储线。每个存储器线的目录条目指示对应的存储器行的副本是否存储在另一个节点的高速缓存存储器系统中。高速缓冲存储器系统存储指示每个存储器线的高速缓存副本是否是专用副本的存储器行的副本和高速缓存状态信息。每个相应节点的逻辑被配置为响应特定存储器线及其对应的目录条目的事务请求，其中相应节点是特定存储器的归属节点。当家庭节点的高速缓冲存储器系统存储特定存储器线的专用副本时，逻辑通过发送从高速缓冲存储器系统检索的特定存储器线的副本和预定义的空目录条目值来响应该请求，因此不从主节点的主存储器检索内存条及其目录条目。

7. 发明授权

US06668308B2 Scalable architecture based on single-chip multiprocessing 有权
公开(公告)号：US06668308B2
公开(公告)日：2003-12-23
申请号：US09877793
申请日：2001-06-08
申请人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
发明人： Luiz Andre Barroso , Kourosh Gharachorloo , Andreas Nowatzyk
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0826 , G06F2212/621
摘要： A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRANHA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.

8. 发明授权

US08933913B2 Electromagnetic 3D stylus 有权
标题翻译：电磁3D手写笔
公开(公告)号：US08933913B2
公开(公告)日：2015-01-13
申请号：US13171324
申请日：2011-06-28
申请人： Andreas Nowatzyk , Charles P. Thacker
发明人： Andreas Nowatzyk , Charles P. Thacker
IPC分类号： G06F3/045 , G06F3/046 , G06F3/0488 , G06F3/01 , G06F3/0354
CPC分类号： G06F3/046 , G06F3/017 , G06F3/03545 , G06F3/0488 , G06F2203/04101
摘要： A stylus system and method for determining the three-dimensional position and orientation of a stylus operating within a volume located above a surface of a display device is described. In some embodiments, the stylus system includes a stylus and a display device. The stylus senses one or more magnetic fields generated from a set of transmitting coils associated with the display device and transmits sensing information over an RF channel to a receiver in the display device. The display device determines the three-dimensional position of the stylus by applying a cell-based position reconstruction technique that compares the received sensing information with predetermined magnetic field values associated with one or more predetermined regions located above the surface of the display device. The cell-based position reconstruction technique accommodates magnetic field distortions due to the presence of conductive elements within or near the display device.
摘要翻译：描述了用于确定在位于显示设备的表面上方的体积内操作的触控笔的三维位置和方位的触控笔系统和方法。在一些实施例中，触笔系统包括触针和显示装置。触笔感测从与显示装置相关联的一组发送线圈产生的一个或多个磁场，并且通过RF信道将感测信息发送到显示装置中的接收器。显示装置通过应用基于单元的位置重建技术来确定触笔的三维位置，该技术将接收到的感测信息与与位于显示装置的表面上方的一个或多个预定区域相关联的预定磁场值进行比较。基于单元的位置重建技术由于在显示装置内或附近存在导电元件而适应磁场失真。

9. 发明申请

US20120206349A1 UNIVERSAL STYLUS DEVICE 有权
标题翻译：通用STYLUS设备
公开(公告)号：US20120206349A1
公开(公告)日：2012-08-16
申请号：US13025165
申请日：2011-02-11
申请人： Andreas Nowatzyk , Charles P. Thacker
发明人： Andreas Nowatzyk , Charles P. Thacker
IPC分类号： G06F3/033
CPC分类号： G06F3/03545 , G06F3/0321
摘要： A stylus device receives light from a display though an optical element that is adapted to increase the field curvature of an image formed on an image sensor of the stylus device. Based on the size and shape of a portion of the image that is in focus, a distance, orientation, and/or azimuth of the stylus device with respect to the display can be determined. In addition, a position corresponding to each pixel, or groups of pixels, is encoded into blue light emitted by each pixel or group of pixels of the display. Upon initialization, or after a loss of synchronization, the stylus device can determine its position with respect to the pixels by decoding the encoded position. After synchronizing its position with the display, the stylus device can determine its subsequent positions by tracking pixels of the display.
摘要翻译：触针装置通过适于增加形成在触针装置的图像传感器上的图像的场曲率的光学元件从显示器接收光。基于对焦的图像的一部分的尺寸和形状，可以确定触针装置相对于显示器的距离，方位和/或方位角。此外，对应于每个像素或像素组的位置被编码成由显示器的每个像素或像素组发射的蓝光。在初始化或者在失去同步之后，触笔装置可以通过解码编码位置来确定其相对于像素的位置。在与显示器同步其位置之后，触笔装置可以通过跟踪显示器的像素来确定其后续的位置。

10. 发明申请

US20120179674A1 HARDWARE ACCELERATED SHORTEST PATH COMPUTATION 有权
标题翻译：硬件加速最短路径计算
公开(公告)号：US20120179674A1
公开(公告)日：2012-07-12
申请号：US12987176
申请日：2011-01-10
申请人： Daniel Delling , Andrew V. Goldberg , Andreas Nowatzyk , Renato F. Werneck
发明人： Daniel Delling , Andrew V. Goldberg , Andreas Nowatzyk , Renato F. Werneck
IPC分类号： G06F17/30
CPC分类号： G06F17/30241 , G01C21/3446 , G06F17/30436 , G06F17/30533
摘要： The non-negative single-source shortest path (NSSP) problem is solved on a graph by using a preprocessing phase and then, in a query phase, computing the distances from a given source in the graph with a linear sweep over all the vertices. Contraction hierarchies may be used in the preprocessing phase and in the query phase. Optimizations may include reordering the vertices in advance to exploit locality, performing multiple NSSP computations simultaneously, marking vertices during initialization, and using parallelism. Techniques may be performed on a graphics processing unit (GPU). This makes applications based on all-pairs shortest-paths practical for continental-sized road networks. The applications include, for example, computing graph diameter, exact arc flags, and centrality measures such as exact reaches or betweenness.
摘要翻译：通过使用预处理阶段，在图上解决非负单源最短路径（NSSP）问题，然后在查询阶段，通过所有顶点的线性扫描计算图中给定源的距离。收缩层次可用于预处理阶段和查询阶段。优化可以包括预先重新排列顶点以利用局部性，同时执行多个NSSP计算，在初始化期间标记顶点并使用并行性。技术可以在图形处理单元（GPU）上执行。这使得基于所有对的最短路径的应用对于大陆路网络是可行的。应用包括例如计算图形直径，精确弧形标记以及诸如精确到达或中间性之类的中心度量度。

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