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1. 发明授权

US09029834B2 Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric 有权
标题翻译：使用牺牲图案化电介质形成用于纳米线的周围栅极的工艺
公开(公告)号：US09029834B2
公开(公告)日：2015-05-12
申请号：US12830514
申请日：2010-07-06
申请人： Sarunya Bangsaruntip , Guy Cohen , Michael A. Guillorn
发明人： Sarunya Bangsaruntip , Guy Cohen , Michael A. Guillorn
IPC分类号： H01L29/775 , H01L21/84 , B82Y10/00 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786 , H01L21/285
CPC分类号： H01L29/0669 , B82Y10/00 , H01L21/28518 , H01L29/0649 , H01L29/0665 , H01L29/165 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/775 , H01L29/7831 , H01L29/78645 , H01L29/78696
摘要： Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.
摘要翻译：提供了在纳米线FET器件中限定镶嵌栅极的技术。一方面，提供一种制造FET器件的方法，包括以下步骤。提供了具有在BOX上的SOI层的SOI晶片。纳米线和焊盘以阶梯状构造在SOI层中图案化。 BOX凹入纳米线下方。在凹入的BOX上形成可图案的电介质伪栅极，并围绕每个纳米线的一部分。 CMP停止层沉积在虚拟栅极和源极和漏极区域上。在CMP停止层上沉积电介质膜。使用CMP对电介质膜进行平面化以暴露虚拟栅极。至少部分地去除虚拟栅极，以便在沟道区域中释放纳米线。虚拟栅极被栅极导体材料代替。

2. 发明申请

US20120007051A1 Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric 有权
标题翻译：使用可牺牲图案电介质形成纳米线周围栅极的工艺
公开(公告)号：US20120007051A1
公开(公告)日：2012-01-12
申请号：US12830514
申请日：2010-07-06
申请人： Sarunya Bangsaruntip , Guy Cohen , Michael A. Guillorn
发明人： Sarunya Bangsaruntip , Guy Cohen , Michael A. Guillorn
IPC分类号： H01L29/775 , H01L21/84
CPC分类号： H01L29/0669 , B82Y10/00 , H01L21/28518 , H01L29/0649 , H01L29/0665 , H01L29/165 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/775 , H01L29/7831 , H01L29/78645 , H01L29/78696
摘要： Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.
摘要翻译：提供了在纳米线FET器件中限定镶嵌栅极的技术。一方面，提供一种制造FET器件的方法，包括以下步骤。提供了具有在BOX上的SOI层的SOI晶片。纳米线和焊盘以阶梯状构造在SOI层中图案化。 BOX凹入纳米线下方。在凹入的BOX上形成可图案的电介质伪栅极，并围绕每个纳米线的一部分。 CMP停止层沉积在虚拟栅极和源极和漏极区域上。在CMP停止层上沉积电介质膜。使用CMP对电介质膜进行平面化以暴露虚拟栅极。至少部分地去除虚拟栅极，以便在沟道区域中释放纳米线。虚拟栅极被栅极导体材料代替。

3. 发明授权

US08936972B2 Epitaxially thickened doped or undoped core nanowire FET structure and method for increasing effective device width 有权
标题翻译：外延增厚的掺杂或未掺杂的核心纳米线FET结构和增加有效器件宽度的方法
公开(公告)号：US08936972B2
公开(公告)日：2015-01-20
申请号：US13596234
申请日：2012-08-28
申请人： Sarunya Bangsaruntip , Guy Cohen , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/84 , H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02428 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.
摘要翻译：提供了增加纳米线FET器件的有效器件宽度的技术。一方面，提供一种制造FET器件的方法。该方法包括以下步骤。提供了在BOX上具有SOI层的SOI晶片，其中SOI层存在于掩埋氮化物层和氮化物盖之间。蚀刻SOI层，埋入氮化物层和氮化物盖，以形成阶梯状构造的SOI层中的纳米线芯和焊盘。纳米线芯悬挂在BOX上。外延侧壁形成在纳米线芯的侧壁上。从纳米线芯中去除掩埋氮化物层和氮化物盖。形成围绕纳米线芯和外延侧壁中的每一个的至少一部分的栅叠层。

4. 发明授权

US08564025B2 Nanowire FET having induced radial strain 有权
标题翻译：纳米线FET引起径向应变
公开(公告)号：US08564025B2
公开(公告)日：2013-10-22
申请号：US13566594
申请日：2012-08-03
申请人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/7845 , H01L29/78696
摘要： An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
摘要翻译：提供了一种中间处理装置，包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线，包括围绕该纳米线的栅极导体和围绕该栅极导体的多晶硅的栅极以及设置成与该栅极导体反应的硅化物形成金属多晶硅以形成完全硅化（FUSI）材料以在纳米线中诱导径向应变。

5. 发明授权

US08324940B2 Nanowire circuits in matched devices 有权
标题翻译：纳米线电路在匹配的设备
公开(公告)号：US08324940B2
公开(公告)日：2012-12-04
申请号：US12758939
申请日：2010-04-13
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H03K19/0948
CPC分类号： H03K19/20 , B82Y10/00 , G11C11/412 , G11C11/54 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/12 , H01L29/0665 , H01L29/0673 , H01L29/775 , H01L29/78696
摘要： An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.
摘要翻译：逆变器装置包括连接到电压源节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一p型场效应晶体管（pFET）器件和第一n型场效应晶体管（nFET ）器件，其具有设置在第一纳米线上的栅极。

6. 发明申请

US20110062411A1 MOSFET with a Nanowire Channel and Fully Silicided (FUSI) Wrapped Around Gate 有权
标题翻译：具有纳米线通道和完全硅化（FUSI）的MOSFET封装在门附近
公开(公告)号：US20110062411A1
公开(公告)日：2011-03-17
申请号：US12561694
申请日：2009-09-17
申请人： Sarunya Bangsaruntip , Guy Cohen
发明人： Sarunya Bangsaruntip , Guy Cohen
IPC分类号： H01L29/12 , H01L21/336 , H01L21/762
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/0676 , H01L29/42392 , H01L29/4908 , H01L29/66439 , H01L29/66628 , H01L29/775 , H01L29/78696
摘要： Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.
摘要翻译：提供纳米线 - 沟道金属氧化物半导体场效应晶体管（MOSFET）及其制造技术。一方面，MOSFET包括纳米线通道; 围绕纳米线通道的完全硅化的栅极; 并且由纳米线通道连接的升高的源极和漏极。还提供了制造MOSFET的方法。

7. 发明授权

US08648330B2 Nanowire field effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US08648330B2
公开(公告)日：2014-02-11
申请号：US13343799
申请日：2012-01-05
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/335 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.
摘要翻译：形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区渠道区域。

8. 发明授权

US08558219B2 Nanowire field effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US08558219B2
公开(公告)日：2013-10-15
申请号：US13606365
申请日：2012-09-07
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L21/335 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.
摘要翻译：形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区渠道区域。

9. 发明授权

US08524544B2 MOSFET with a nanowire channel and fully silicided (FUSI) wrapped around gate 有权
标题翻译：具有纳米线通道和全硅化物（FUSI）的MOSFET缠绕在栅极上
公开(公告)号：US08524544B2
公开(公告)日：2013-09-03
申请号：US13468307
申请日：2012-05-10
申请人： Sarunya Bangsaruntip , Guy Cohen
发明人： Sarunya Bangsaruntip , Guy Cohen
IPC分类号： H01L21/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/0676 , H01L29/42392 , H01L29/4908 , H01L29/66439 , H01L29/66628 , H01L29/775 , H01L29/78696
摘要： Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.
摘要翻译：提供纳米线 - 沟道金属氧化物半导体场效应晶体管（MOSFET）及其制造技术。一方面，MOSFET包括纳米线通道; 围绕纳米线通道的完全硅化的栅极; 并且由纳米线通道连接的升高的源极和漏极。还提供了制造MOSFET的方法。

10. 发明申请

US20120280206A1 Nanowire Circuits in Matched Devices 有权
标题翻译：匹配器件中的纳米线电路
公开(公告)号：US20120280206A1
公开(公告)日：2012-11-08
申请号：US13554057
申请日：2012-07-20
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L27/085 , H01L21/8232
CPC分类号： H03K19/20 , B82Y10/00 , G11C11/412 , G11C11/54 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/12 , H01L29/0665 , H01L29/0673 , H01L29/775 , H01L29/78696
摘要： A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.
摘要翻译：存储器件包括连接到第一位线节点和接地节点的第一纳米线，具有设置在第一纳米线上的栅极的第一场效应晶体管（FET），具有设置在第一纳米线上的栅极的第二FET，连接到电压源节点和第一输入节点的纳米线，具有设置在第二纳米线上的栅极的第三FET，连接到电压源节点的第三纳米线和第二输入节点，具有设置在第三纳米线上的栅极的第四FET 纳米线，连接到第二位线节点的第四纳米线和所述接地节点，具有设置在所述第四纳米线上的栅极的第五FET以及设置在所述第四纳米线上的栅极的第六FET。

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