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1. 发明授权

US5500551A Integrated emitter switching configuration using bipolar transistors 失效
标题翻译：使用双极晶体管的集成发射极开关配置
公开(公告)号：US5500551A
公开(公告)日：1996-03-19
申请号：US273589
申请日：1994-07-11
申请人： Santo Puzzolo , Raffaele Zambrano , Mario Paparo
发明人： Santo Puzzolo , Raffaele Zambrano , Mario Paparo
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/732 , H01L29/00
CPC分类号： H01L27/0823 , H01L21/8222 , H01L27/0825
摘要： A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.
摘要翻译：双极功率晶体管和低电压双极晶体管以集成结构组合在发射极开关或半谐振器配置中。在具有非隔离部件的版本中，结构的部件彼此完全或部分地叠置，部分地在第一外延层中，部分地叠置在第二外延层中，并且低电压双极晶体管位于双极功率晶体管因此是完全埋入的有源结构。在具有隔离元件的版本中，在N外延层中有两个P +区。第一P +区域构成功率晶体管基极并且包围功率晶体管的N +发射极区域。第二P +区域包围分别构成低压晶体管的集电极，发射极和基极区域的两个N +区域和一个P +区域。芯片前面的金属化提供了低压晶体管的集电极触点和功率晶体管的发射极触点之间的连接。

2. 发明授权

US5866461A Method for forming an integrated emitter switching configuration using bipolar transistors 失效
标题翻译：使用双极晶体管形成集成发射极开关配置的方法
公开(公告)号：US5866461A
公开(公告)日：1999-02-02
申请号：US801584
申请日：1997-02-18
申请人： Santo Puzzolo , Raffaele Zambrano , Mario Paparo
发明人： Santo Puzzolo , Raffaele Zambrano , Mario Paparo
IPC分类号： H01L27/07 , H01L27/082 , H01L21/8228
CPC分类号： H01L27/0744 , H01L27/0823
摘要： A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.
摘要翻译：双极功率晶体管和低电压双极晶体管以集成结构组合在发射极开关或半谐振器配置中。在具有非隔离部件的版本中，结构的部件彼此完全或部分地叠置，部分地在第一外延层中，部分地叠置在第二外延层中，并且低电压双极晶体管位于双极功率晶体管因此是完全埋入的有源结构。在具有隔离元件的版本中，在N-外延层中有两个P +区。第一P +区域构成功率晶体管基极并且包围功率晶体管的N +发射极区域。第二P +区域包围分别构成低压晶体管的集电极，发射极和基极区域的两个N +区域和一个P +区域。芯片前面的金属化提供了低压晶体管的集电极触点和功率晶体管的发射极触点之间的连接。

3. 发明授权

US5376821A Integrated emitter switching configuration using bipolar transistors 失效
标题翻译：使用双极晶体管的集成发射极开关配置
公开(公告)号：US5376821A
公开(公告)日：1994-12-27
申请号：US812704
申请日：1991-12-23
申请人： Santo Puzzolo , Raffaele Zambrano , Mario Paparo
发明人： Santo Puzzolo , Raffaele Zambrano , Mario Paparo
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/732 , H01L27/07
CPC分类号： H01L27/0823 , H01L21/8222 , H01L27/0825
摘要： A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N-epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.
摘要翻译：双极功率晶体管和低电压双极晶体管以集成结构组合在发射极开关或半谐振器配置中。在具有非隔离部件的版本中，结构的部件彼此完全或部分地叠置，部分地在第一外延层中，部分地叠置在第二外延层中，并且低电压双极晶体管位于双极功率晶体管因此是完全埋入的有源结构。在具有隔离元件的版本中，N外延层中有两个P +区。第一P +区域构成功率晶体管基极并且包围功率晶体管的N +发射极区域。第二P +区域包围分别构成低压晶体管的集电极，发射极和基极区域的两个N +区域和一个P +区域。芯片前面的金属化提供了低压晶体管的集电极触点和功率晶体管的发射极触点之间的连接。

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