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    • 4. 发明授权
    • Inductance mitigation through switching density analysis
    • 通过开关密度分析减小电感
    • US08060846B2
    • 2011-11-15
    • US11732950
    • 2007-04-04
    • Stuart A. TaylorEdward M. RoseboomSimon Burke
    • Stuart A. TaylorEdward M. RoseboomSimon Burke
    • G06F17/50
    • G06F17/5031G06F2217/62
    • Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock are compared to the density of wires will not switch within that same time. Regions of the chip that have a high ratio of density of switching wires versus non-switching wires are determined to have the potential of an inductive coupling problem. Additional grounded metal is added into the problematic regions of the chip to improve the switching versus non-switching wire density.
    • 描述了用于检测高密度集成电路设计中的电感耦合的潜在面积的方法的实施例。 电感减轻过程首先将归纳分析转换为密度问题。 在系统时钟的一部分内切换的区域内的线的密度与电线的密度进行比较将不会在同一时间内转换。 确定开关线与非开关线之间的高密度比的芯片的区域具有电感耦合问题的潜力。 额外的接地金属被添加到芯片的有问题的区域中以改善开关与非开关线密度。