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1. 发明申请

US20180285191A1 REFERENCE VOLTAGE CONTROL BASED ON ERROR DETECTION 审中-公开
公开(公告)号：US20180285191A1
公开(公告)日：2018-10-04
申请号：US15477050
申请日：2017-04-01
申请人： Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Eric C. Samson , Joydeep Ray , Travis T. Schluessler , Jacek Kwiatkowski , Abhishek R. Appu , Ankur N. Shah , Altug Koker
发明人： Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Eric C. Samson , Joydeep Ray , Travis T. Schluessler , Jacek Kwiatkowski , Abhishek R. Appu , Ankur N. Shah , Altug Koker
IPC分类号： G06F11/07
摘要： Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.

2. 发明申请

US20180300238A1 ADAPTIVE CACHE SIZING PER WORKLOAD 审中-公开
公开(公告)号：US20180300238A1
公开(公告)日：2018-10-18
申请号：US15488637
申请日：2017-04-17
申请人： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F12/06
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

3. 发明申请

US20180285158A1 HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS 审中-公开
公开(公告)号：US20180285158A1
公开(公告)日：2018-10-04
申请号：US15477026
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
发明人： Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
IPC分类号： G06F9/50 , G06T1/60 , G06T1/20 , G06T15/00 , G06F9/48 , G06F1/32
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

4. 发明授权

US09727388B2 Migrating threads between asymmetric cores in a multiple core processor 有权
公开(公告)号：US09727388B2
公开(公告)日：2017-08-08
申请号：US13995340
申请日：2011-12-29
申请人： Sanjeev S. Jahagirdar , Varghese George , Inder Sodhi
发明人： Sanjeev S. Jahagirdar , Varghese George , Inder Sodhi
IPC分类号： G06F9/50 , G06F9/30 , G06F9/48
CPC分类号： G06F9/5083 , G06F9/30003 , G06F9/4856
摘要： Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

5. 发明申请

US20140032950A1 METHOD, APPARATUS, AND SYSTEM FOR OPTIMIZING FREQUENCY AND PERFORMANCE IN A MULTIDIE MICROPROCESSOR 有权
公开(公告)号：US20140032950A1
公开(公告)日：2014-01-30
申请号：US14041688
申请日：2013-09-30
申请人： Jose P. Allarey , Varghese George , Sanjeev S. Jahagirdar , Oren Lamdan , Ofer Nathan , Tomer Ziv
发明人： Jose P. Allarey , Varghese George , Sanjeev S. Jahagirdar , Oren Lamdan , Ofer Nathan , Tomer Ziv
IPC分类号： G06F1/20
CPC分类号： G06F15/82 , G06F1/08 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F9/06 , G06F9/30145 , G06F15/76 , Y02D10/126 , Y02D10/16
摘要： With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

6. 发明申请

US20120198207A1 ASYMMETRIC PERFORMANCE MULTICORE ARCHITECTURE WITH SAME INSTRUCTION SET ARCHITECTURE 有权
标题翻译：具有相同指令集架构的不对称性能多体建筑
公开(公告)号：US20120198207A1
公开(公告)日：2012-08-02
申请号：US13335257
申请日：2011-12-22
申请人： Varghese George , Sanjeev S. Jahagirdar , Deborah T. Marr
发明人： Varghese George , Sanjeev S. Jahagirdar , Deborah T. Marr
IPC分类号： G06F15/76
CPC分类号： G06F15/80 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F9/5094 , G06F13/4022 , Y02D10/122 , Y02D10/151 , Y02D10/22
摘要： A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
摘要翻译：描述了一种方法，其涉及多核处理器的操作使能的核，使得两个核以相同的指令集支持相应的软件例程，第一核具有更高的性能并且在相同的一组应用供给下消耗比第二个核的更多的功率电压和工作频率。

7. 发明申请

US20150177798A1 CONFIGURABLE POWER SUPPLIES FOR DYNAMIC CURRENT SHARING 有权
标题翻译：用于动态电流共享的可配置电源
公开(公告)号：US20150177798A1
公开(公告)日：2015-06-25
申请号：US14138550
申请日：2013-12-23
申请人： Sandeep K. Venishetti , Sanjeev S. Jahagirdar , Srinivas Thota
发明人： Sandeep K. Venishetti , Sanjeev S. Jahagirdar , Srinivas Thota
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/189 , G06F1/263 , G06F1/3287 , H02J2003/001 , Y02D10/171 , Y10T307/352
摘要： An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a second voltage source, and to deliver power to each of a plurality of electronic circuitry blocks (ECBs), including to deliver first ECB power to a first ECB and second ECB power to a second ECB. The first ECB power includes a first portion of the first power and a first portion of the second power. The apparatus also includes power management logic to dynamically adjust the power to be provided to each ECB. Responsive to a change in a first activity level of the first ECB, the power management logic is to change the first ECB power by adjustment of the first portion of the first power and adjustment of the first portion of the second power. Other embodiments are described and claimed.
摘要翻译：一种设备包括分配网络，其包括被配置为从第一电压源接收第一功率的电路和来自第二电压源的第二功率，并且向多个电子电路模块（ECB）中的每一个发送功率，包括递送第一ECB 第一个欧洲央行的权力和第二个欧洲央行的第二个ECB的权力。第一ECB功率包括第一功率的第一部分和第二功率的第一部分。该装置还包括电源管理逻辑以动态地调整要提供给每个ECB的功率。响应于第一ECB的第一活动级别的改变，电源管理逻辑是通过调整第一功率的第一部分并调整第二功率的第一部分来改变第一ECB功率。描述和要求保护其他实施例。

8. 发明申请

US20140359311A1 Controlling Power Delivery To A Processor Via A Bypass 有权
标题翻译：通过旁路控制处理器的电力输送
公开(公告)号：US20140359311A1
公开(公告)日：2014-12-04
申请号：US13906652
申请日：2013-05-31
申请人： Sanjeev S. Jahagirdar , Satish K. Damaraju , Yun-Han Chen , Ryan D. Wells , Inder M. Sodhi , Vishram Sarurkar , Ken Drottar , Ashish V. Choubal , Rabiul Islam
发明人： Sanjeev S. Jahagirdar , Satish K. Damaraju , Yun-Han Chen , Ryan D. Wells , Inder M. Sodhi , Vishram Sarurkar , Ken Drottar , Ashish V. Choubal , Rabiul Islam
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/152 , Y02D10/172 , Y02D10/22
摘要： In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个域，每个域以独立可控的电压和频率工作，多个线性稳压器各自接收来自芯片外源的第一电压并可控制以将调节电压提供给至少一个以及多个选择器，每个选择器都耦合到所述域中的一个，其中每个选择器被配置为从所述线性调节器之一提供调节电压或将旁路电压提供给相应的域。描述和要求保护其他实施例。

9. 发明申请

US20140189225A1 Independent Control Of Processor Core Retention States 有权
标题翻译：处理器核心保留状态的独立控制
公开(公告)号：US20140189225A1
公开(公告)日：2014-07-03
申请号：US13729833
申请日：2012-12-28
申请人： Shaun M. Conrad , Stephen H. Gunther , Jeremy J. Shrall , Anant S. Deval , Sanjeev S. Jahagirdar
发明人： Shaun M. Conrad , Stephen H. Gunther , Jeremy J. Shrall , Anant S. Deval , Sanjeev S. Jahagirdar
IPC分类号： G06F1/32 , G11C7/10
CPC分类号： G06F1/3296 , G06F1/3243 , Y02D10/152 , Y02D10/172
摘要： In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括第一处理器核心，第二处理器核心，第一电压调节器，以在第一处理器核心活动时向第一处理器核心提供具有第一有效值的第一电压;以及第二电压调节器，当第二处理器核心活动时，向第二处理器核心提供具有第二有效值的第二电压。响应于将第一处理器核放置在具有相关联的第一低功率电压值的第一低功率状态的请求，第一电压调节器将第一电压降低到小于第一低功率电压的第二低功率电压值电压值，独立于第二电压调节器。存储在第一处理器核心的第一寄存器中的第一数据保持在第二低功率值。描述和要求保护其他实施例。

10. 发明申请

US20120159074A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC CACHE SIZING AND CACHE OPERATING VOLTAGE MANAGEMENT FOR OPTIMAL POWER PERFORMANCE 有权
标题翻译：用于能源效率和能源保护的方法，装置和系统，包括动态高速缓存和高速运行电压管理，实现最佳功率性能
公开(公告)号：US20120159074A1
公开(公告)日：2012-06-21
申请号：US13336977
申请日：2011-12-23
申请人： Inder M. Sodhi , Satish K. Damaraju , Sanjeev S. Jahagirdar , Ryan D. Wells
发明人： Inder M. Sodhi , Satish K. Damaraju , Sanjeev S. Jahagirdar , Ryan D. Wells
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172
摘要： Embodiments of the invention relate to increased energy efficiency and conservation by reducing and increasing an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.
摘要翻译：本发明的实施例涉及通过减少和增加可供由处理器使用的高速缓存量和提供给高速缓存和处理器的功率量来提高能量效率和节约，基于实际使用的缓存量处理器处理数据。例如，功率控制单元（PCU）可以监视最后一级高速缓存（LLC）以识别处理器正在使用的高速缓存的大小或数量来处理数据，并且基于该量来确定启发式。基于所使用的缓存的监视量和启发式，PCU引起可用于处理器的缓存的量的相应减少或增加，并且相应地降低或增加提供给高速缓存的功率量，以及到处理器。

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