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1. 发明授权

US07986251B2 Input/output (IO) interface and method of transmitting IO data 失效
标题翻译：输入/输出（IO）接口和传输IO数据的方法
公开(公告)号：US07986251B2
公开(公告)日：2011-07-26
申请号：US12547204
申请日：2009-08-25
申请人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
IPC分类号： H03M5/00
CPC分类号： H03M5/06 , G11C7/1006
摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
摘要翻译：输入/输出（IO）接口包括数据编码器，其对具有不同定时的多条并行数据中的每一条进行编码并产生多条编码数据;以及交流（AC）耦合传输单元，其传输多个的交流耦合方法中的编码数据。数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

2. 发明授权

US08321640B2 Data mask system and data mask method 有权
标题翻译：数据掩码系统和数据掩码法
公开(公告)号：US08321640B2
公开(公告)日：2012-11-27
申请号：US12780986
申请日：2010-05-17
申请人： Sang-hyup Kwak , Kwang-il Park , Seung-jun Bae
发明人： Sang-hyup Kwak , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F12/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C11/4096
摘要： A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information.
摘要翻译：数据掩模系统包括提供包括命令信号，地址信号和数据信号的控制信号的处理器，接收控制信号的数据掩码处理器，并响应于控制信号提供写数据或屏蔽数据，并产生数据来自至少一个控制信号的掩模信息和数据掩模选择信号，以及接收数据掩码选择信号的数据掩码寄存器单元，存储数据掩码信息，响应于数据选择存储的数据掩码信息的子集掩模选择信号，并将选择的数据掩码信息返回到数据掩码处理器。数据掩模处理器从数据掩码寄存器单元接收所选择的数据掩码信息，并根据所选择的数据掩码信息提供作为数据信号的数据掩码操作的结果的掩蔽数据。

3. 发明申请

US20100045491A1 INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA 失效
标题翻译：输入/输出（IO）接口和传输IO数据的方法
公开(公告)号：US20100045491A1
公开(公告)日：2010-02-25
申请号：US12547204
申请日：2009-08-25
申请人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
IPC分类号： H03M7/00
CPC分类号： H03M5/06 , G11C7/1006
摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
摘要翻译：输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个的交流耦合方法中的编码数据。数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

4. 发明授权

US08390317B2 Bidirectional equalizer with CMOS inductive bias circuit 有权
标题翻译：带CMOS感应偏置电路的双向均衡器
公开(公告)号：US08390317B2
公开(公告)日：2013-03-05
申请号：US12832212
申请日：2010-07-08
申请人： Seung-jun Bae , Young-sik Kim , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-sik Kim , Sang-hyup Kwak
IPC分类号： H03K19/0175
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1057 , G11C7/1084 , H03K19/018521
摘要： An integrated circuit (IC) device, system and related method of communicating data are described. The IC device includes; a data port configured to provide output data to a channel and receive input data from the channel, an impedance matching circuit connected to the data port and configured to operate as an output driver circuit when the output data is being transmitted and as an on die termination circuit when the input data is being received, and an active inductive bias circuit connected to the data port in parallel with the impedance matching circuit, and configured to adjust the impedance of the data port to the channel during transmission of the output data as a function of output data frequency and adjust the impedance of the data port to the channel during receipt of the input data as a function of input data frequency.
摘要翻译：描述了一种用于传送数据的集成电路（IC）装置，系统和相关方法。 IC器件包括：数据端口，被配置为向通道提供输出数据并从所述通道接收输入数据;阻抗匹配电路，连接到所述数据端口，并且被配置为当所述输出数据被发送时作为输出驱动器电路工作，并且作为管芯端接接收输入数据时的电路以及与阻抗匹配电路并联连接到数据端口的有源感应偏置电路，并且被配置为在输出数据作为功能的传输期间调整数据端口到通道的阻抗的输出数据频率，并根据输入数据频率调整输入数据接收期间数据端口到通道的阻抗。

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