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1. 发明申请

US20160035423A1 NONVOLATILE MEMORY DEVICE AND WORLDLINE DRIVING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其驱动方法
公开(公告)号：US20160035423A1
公开(公告)日：2016-02-04
申请号：US14741224
申请日：2015-06-16
申请人： Sang-Wan NAM , Sun-Min YUN , Bongsoon LIM , Yoon-Hee CHOI
发明人： Sang-Wan NAM , Sun-Min YUN , Bongsoon LIM , Yoon-Hee CHOI
IPC分类号： G11C16/08 , G11C16/10 , G11C16/28 , G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/3459
摘要： According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.
摘要翻译：根据发明构思的示例实施例，非易失性存储器件包括存储单元阵列，地址解码器，输入/输出电路，电压产生电路和控制逻辑。存储单元阵列包括在衬底上的多个存储块。每个存储块包括连接在位线和公共源极线之间的多个串。地址解码器被配置为测量所选择的存储器块的字线的阻抗信息。电压产生电路被配置为产生要施加到字线的字线电压，并且字线电压中的至少一个包括偏移电压和目标电压。控制逻辑被配置为根据测得的字线的阻抗信息来调整偏移电压和偏移时间的电平。

2. 发明申请

US20150370705A1 ADDRESS SCHEDULING METHODS FOR NON-VOLATILE MEMORY DEVICES WITH THREE-DIMENSIONAL MEMORY CELL ARRAYS 审中-公开
标题翻译：具有三维存储器单元阵列的非易失性存储器件的地址调度方法
公开(公告)号：US20150370705A1
公开(公告)日：2015-12-24
申请号：US14837857
申请日：2015-08-27
申请人： Chi Weon YOON , Dong Hyuk CHAE , Sang-Wan NAM , Jung-Yun YUN
发明人： Chi Weon YOON , Dong Hyuk CHAE , Sang-Wan NAM , Jung-Yun YUN
IPC分类号： G06F12/06 , G06F3/06
CPC分类号： G06F12/0646 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
摘要翻译：至少一个地址调度方法包括选择第一位线，选择连接到第一位线的第一串，在第一串中的每个多电平单元的N页上从底部字线到顶部执行地址调度字线，并且在完成第一串中的所有字线上的地址调度之后，以与对第一字符串执行的相同的方式依次执行第二至第K个字符串的地址调度，其中“k”为2或自然数大于2。

3. 发明申请

US20150221387A1 NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
公开(公告)号：US20150221387A1
公开(公告)日：2015-08-06
申请号：US14681748
申请日：2015-04-08
申请人： Sang-Wan NAM
发明人： Sang-Wan NAM
IPC分类号： G11C16/34 , G11C16/26
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C16/3459 , H01L27/11582
摘要： According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.

4. 发明申请

US20130279262A1 NONVOLATILE MEMORY DEVICES, CHANNEL BOOSTING METHODS THEREOF, PROGRAMMING METHODS THEREOF, AND MEMORY SYSTEMS INCLUDING THE SAME 有权
标题翻译：非易失性存储器件，其通道提升方法，其编程方法和包括其中的存储器系统
公开(公告)号：US20130279262A1
公开(公告)日：2013-10-24
申请号：US13920691
申请日：2013-06-18
申请人： ChiWeon YOON , Donghyuk CHAE , Sang-Wan NAM , Sung-Won YUN
发明人： ChiWeon YOON , Donghyuk CHAE , Sang-Wan NAM , Sung-Won YUN
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.
摘要翻译：非易失性存储器件通道升压方法，其中至少两个串连接到一个位线，所述通道升压方法包括将初始通道电压施加到所选存储器块中的串的通道，每个具有未编程的浮动禁止串字符串之间的单元格，以及浮动禁止字符串的增强通道。

5. 发明申请

US20130016561A1 ERASE SYSTEM AND METHOD OF NONVOLATILE MEMORY DEVICE 有权
公开(公告)号：US20130016561A1
公开(公告)日：2013-01-17
申请号：US13478569
申请日：2012-05-23
申请人： Sang-Wan NAM
发明人： Sang-Wan NAM
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/14 , G11C16/16 , G11C16/26 , G11C16/3445 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage.

6. 发明申请

US20160254054A1 NONVOLATILE MEMORY DEVICES AND DRIVING METHODS THEREOF 审中-公开
公开(公告)号：US20160254054A1
公开(公告)日：2016-09-01
申请号：US15152692
申请日：2016-05-12
申请人： Kyung-Hwa KANG , Sang-Wan NAM , Donghyuk CHAE , ChiWeon YOON
发明人： Kyung-Hwa KANG , Sang-Wan NAM , Donghyuk CHAE , ChiWeon YOON
IPC分类号： G11C16/04 , H01L27/115 , H01L23/528 , G11C16/24 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

7. 发明申请

US20150262686A1 ERASE SYSTEM AND METHOD OF NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件的擦除系统和方法
公开(公告)号：US20150262686A1
公开(公告)日：2015-09-17
申请号：US14723525
申请日：2015-05-28
申请人： Sang-Wan NAM
发明人： Sang-Wan NAM
IPC分类号： G11C16/14 , G11C16/34 , G11C16/26
CPC分类号： G11C16/14 , G11C16/16 , G11C16/26 , G11C16/3445 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage.
摘要翻译：非易失性存储器件的擦除系统和方法包括向非易失性存储器的多个存储单元提供擦除电压，对多个存储器单元的字线执行读取电压读取操作，并执行擦除验证操作具有擦除验证电压至所述多个存储单元中的至少一个字线，所述擦除验证电压低于读取电压。

8. 发明申请

US20150078087A1 CONTROL METHOD OF NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件的控制方法
公开(公告)号：US20150078087A1
公开(公告)日：2015-03-19
申请号：US14546477
申请日：2014-11-18
申请人： Sunil SHIM , Jin-Man HAN , Sang-Wan NAM , Won-Taeck JUNG
发明人： Sunil SHIM , Jin-Man HAN , Sang-Wan NAM , Won-Taeck JUNG
IPC分类号： G11C16/34 , G11C16/14
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/349 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block.
摘要翻译：根据示例性实施例，一种非易失性存储器件的控制方法，其包括在衬底上的多个存储块，每个存储块包括沿垂直于衬底的方向堆叠的多个子块，并且被配置为独立擦除，每个子块包括在垂直于衬底的方向上堆叠的多个存储单元。控制方法包括将第一存储块的计数值与参考值进行比较，所述计数值根据在第一存储器块中的数据被编程之后在第一存储器块执行的程序，读取或擦除操作的数量确定; 并且如果所述计数值大于或等于所述参考值，则执行重新编程操作，其中在第一存储器块中编程的数据被读取并且所读取的数据被编程在第二存储器块中。

9. 发明申请

US20140310448A1 METHOD OF OPERATING MEMORY CONTROLLER AND DATA STORAGE DEVICE INCLUDING MEMORY CONTROLLER 有权
标题翻译：操作存储器控制器的方法和包括存储器控制器的数据存储设备
公开(公告)号：US20140310448A1
公开(公告)日：2014-10-16
申请号：US14073155
申请日：2013-11-06
申请人： Sang-Wan NAM , Kitae PARK
发明人： Sang-Wan NAM , Kitae PARK
IPC分类号： G06F12/02
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/1402 , G11C11/5628 , G11C16/3445 , G11C16/3495 , G11C29/52
摘要： In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a block of the memory. The block of the memory includes the selected page. The program/erase cycle count indicates a number of times the block has been erased. The status is selected from a plurality of status states. The status states include a normal state, a weak state and a bad state.
摘要翻译：在一个实施例中，该方法包括基于存储器块的编程/擦除周期计数在存储器控制器处确定所选择的存储器页的状态。存储器的块包括所选择的页面。程序/擦除周期计数指示块已被擦除的次数。该状态是从多个状态中选择的。状态包括正常状态，弱状态和坏状态。

10. 发明申请

US20130170297A1 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失性存储器件和包括其的存储器系统
公开(公告)号：US20130170297A1
公开(公告)日：2013-07-04
申请号：US13619118
申请日：2012-09-14
申请人： Sang-Wan NAM , Kyung-Hwa KANG , Junghoon PARK
发明人： Sang-Wan NAM , Kyung-Hwa KANG , Junghoon PARK
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11582
摘要： According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.
摘要翻译：根据示例性实施例，非易失性存储器件包括第一和第二NAND串。第一NAND串包括第一串选择晶体管，第一局部地和第一全局接地选择晶体管，以及沿垂直于衬底的方向堆叠的第一存储单元。第二NAND串包括第二串选择晶体管，第二局部地和第二全局接地选择晶体管，以及沿与基板垂直的方向堆叠的第二存储单元。该器件包括选择线驱动器，其包括被配置为选择并向第一和第二串选择晶体管，第一和第二局部和全局地选择晶体管提供至少一个操作电压的路径晶体管。第一和第二串选择晶体管彼此电绝缘，并且第一和第二全局接地选择晶体管电连接。

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