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    • 2. 发明授权
    • Method and apparatus for generating a low-density parity check code
    • 用于生成低密度奇偶校验码的方法和装置
    • US07536623B2
    • 2009-05-19
    • US11289300
    • 2005-11-30
    • Sang-Hyo KimHan-Ju KimMin-Goo KimYoung-Mo Gu
    • Sang-Hyo KimHan-Ju KimMin-Goo KimYoung-Mo Gu
    • H03M13/13
    • H03M13/6362H03M13/116H03M13/118H03M13/1185H03M13/1188
    • A low density parity check (LDPC) code generating method and apparatus are provided. A parity check matrix with (N−K) rows for check nodes and N columns for variable nodes are formed to encode an information sequence of length K to a codeword of length N. The parity check matrix is divided into an information part matrix with K columns and a parity part matrix with (N−k) columns. The parity part is divided into P×P subblocks. P is a divisor of (N−K). First and second diagonals are defined in the parity part matrix and the second diagonal is a shift of the first diagonal by f subblocks. Shifted identity matrices are placed on the first and second diagonals and zero matrices are filled elsewhere. An odd number of delta matrices each having only one element of 1 are placed in one subblock column of the parity part matrix. The parity check matrix is stored.
    • 提供了一种低密度奇偶校验(LDPC)码生成方法和装置。 形成具有用于校验节点的(NK)行和用于可变节点的N列的奇偶校验矩阵,以将长度为K的信息序列编码为长度为N的码字。奇偶校验矩阵被划分为具有K列的信息部分矩阵, 具有(Nk)列的奇偶校验部分矩阵。 奇偶校验部分分为PxP子块。 P是(N-K)的除数。 在奇偶校验部分矩阵中定义第一和第二对角线,第二对角线是第一对角线由f子块的移位。 移位的身份矩阵放置在第一和第二个对角线上,零矩阵填充到别处。 每个仅具有1个元素的奇数数量的Δ矩阵被放置在奇偶校验部分矩阵的一个子块列中。 存储奇偶校验矩阵。
    • 3. 发明申请
    • Apparatus and method for decoding burst in an OFDMA mobile communication system
    • 用于在OFDMA移动通信系统中解码突发的装置和方法
    • US20070079215A1
    • 2007-04-05
    • US11519779
    • 2006-09-13
    • Han-Ju KimYoung-Mo GuDong-Woon JungMin-Goo Kim
    • Han-Ju KimYoung-Mo GuDong-Woon JungMin-Goo Kim
    • H03M13/00
    • H04L27/2647H04L1/0054H04L1/0059H04L1/0071H04L1/0072H04L1/08H04L5/023
    • A decoding apparatus in an Orthogonal Frequency Division Multiple Access (OFDMA) mobile communication system is provided. In the apparatus comprises, a first combiner performs first combining on an input burst a first number of times. A deinterleaver deinterleaves an output of the first combiner and outputs a burst having a repeated structure. A second combiner performs second combining on the burst having the repeated structure a second number of times. A decoder decodes the combined burst. A signal detector stores a second internal memory state value of the decoder for an instance where a first decoded bit is extracted from the decoded data, stores a second internal memory state value of the decoder for an instance where a last decoded bit is extracted from the decoded data, compares the first and second stored internal memory state values of the decoder, and sets a burst quality indicator (BQI) according to the comparison result.
    • 提供了一种正交频分多址(OFDMA)移动通信系统中的解码装置。 在该装置中,第一组合器在输入突发上执行第一次合并。 解交织器对第一组合器的输出进行解交织并输出具有重复结构的脉冲串。 第二组合器在具有重复结构的脉冲串上执行第二次组合第二次。 解码器解码组合突发。 信号检测器存储解码器的第二内部存储器状态值,用于从解码数据中提取第一解码位的情况,存储解码器的第二内部存储器状态值,用于从其中提取最后一个解码位的情况 解码数据,比较解码器的第一和第二存储的内部存储器状态值,并根据比较结果设置突发质量指示符(BQI)。
    • 4. 发明授权
    • Apparatus and method for decoding burst in an OFDMA mobile communication system
    • 用于在OFDMA移动通信系统中解码突发的装置和方法
    • US07747931B2
    • 2010-06-29
    • US11519779
    • 2006-09-13
    • Han-Ju KimYoung-Mo GuDong-Woon JungMin-Goo Kim
    • Han-Ju KimYoung-Mo GuDong-Woon JungMin-Goo Kim
    • H03M13/03
    • H04L27/2647H04L1/0054H04L1/0059H04L1/0071H04L1/0072H04L1/08H04L5/023
    • A decoding apparatus in an Orthogonal Frequency Division Multiple Access (OFDMA) mobile communication system is provided. In the apparatus comprises, a first combiner performs first combining on an input burst a first number of times. A deinterleaver deinterleaves an output of the first combiner and outputs a burst having a repeated structure. A second combiner performs second combining on the burst having the repeated structure a second number of times. A decoder decodes the combined burst. A signal detector stores a second internal memory state value of the decoder for an instance where a first decoded bit is extracted from the decoded data, stores a second internal memory state value of the decoder for an instance where a last decoded bit is extracted from the decoded data, compares the first and second stored internal memory state values of the decoder, and sets a burst quality indicator (BQI) according to the comparison result.
    • 提供了一种正交频分多址(OFDMA)移动通信系统中的解码装置。 在该装置中,第一组合器在输入突发上执行第一次合并。 解交织器对第一组合器的输出进行解交织并输出具有重复结构的脉冲串。 第二组合器在具有重复结构的脉冲串上执行第二次组合第二次。 解码器解码组合突发。 信号检测器存储解码器的第二内部存储器状态值,用于从解码数据中提取第一解码位的情况,存储解码器的第二内部存储器状态值,用于从其中提取最后一个解码位的情况 解码数据,比较解码器的第一和第二存储的内部存储器状态值,并根据比较结果设置突发质量指示符(BQI)。
    • 5. 发明申请
    • Method and apparatus for efficiently decoding low density parity check code
    • 用于有效解码低密度奇偶校验码的方法和装置
    • US20060107193A1
    • 2006-05-18
    • US11247188
    • 2005-10-12
    • Sung-Jin ParkSang-Hyo KimHan-Ju KimMin-Goo Kim
    • Sung-Jin ParkSang-Hyo KimHan-Ju KimMin-Goo Kim
    • G06F11/00H03M13/00
    • H03M13/1145H03M13/1105H03M13/1111H03M13/1134H03M13/1137
    • A method and apparatus are provided for decoding a forward error correction code in a mobile communication system using a LDPC code. A check node processor performs check node processing on information received with a plurality of check nodes and an accumulator accumulates check node output values from the check node processor with previous accumulated values. An edge memory stores the check node output values, and two accumulation memories separately store accumulated values from the accumulator and the previous accumulated values. A subtractor subtracts the check node output values from the accumulated values, and a hard-decision block performs hard-decision on the received information and the output value of the subtractor. A bit buffer stores the hard-decision result, and a parity check block performs parity check on the hard-decision result to determine whether to stop iterative decoding. A multiplexer delivers the subtraction result values to both the check node processor and the hard-decision block.
    • 提供一种用于使用LDPC码对移动通信系统中的前向纠错码进行解码的方法和装置。 校验节点处理器对由多个校验节点接收的信息执行校验节点处理,并且累加器从具有先前累积值的校验节点处理器累加校验节点输出值。 边缘存储器存储校验节点输出值,并且两个累积存储器分别存储来自累加器的累加值和先前累积值。 减法器从累加值中减去校验节点输出值,硬判决块对接收到的信息和减法器的输出值进行硬判决。 位缓冲器存储硬判决结果,奇偶校验块对硬判决结果执行奇偶校验,以确定是否停止迭代解码。 多路复用器将减法结果值递送给校验节点处理器和硬判决块。
    • 6. 发明授权
    • Method and apparatus for decoding low density parity check code using united node processing
    • 使用联合节点处理解码低密度奇偶校验码的方法和装置
    • US07454685B2
    • 2008-11-18
    • US11283732
    • 2005-11-22
    • Sang-Hyo KimSung-Jin ParkHan-Ju KimMin-Goo Kim
    • Sang-Hyo KimSung-Jin ParkHan-Ju KimMin-Goo Kim
    • H03M13/00
    • H03M13/1137H03M13/1114H03M13/114H03M13/116
    • A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.
    • 提供了一种解码包括多个校验节点和多个可变节点的LDPC码的方法和装置。 该装置包括校验节点选择调度器,该校验节点选择调度器选择校验节点中的至少一个,将可变节点的输入LLR值存储为初始LLR值的LLR存储器,并且存储用于连接到所选校验节点的变量节点的更新的LLR值 以及检查节点消息存储器,其将选择的校验节点上指示校验节点处理的结果值的校验节点消息存储。 该装置还包括至少一个联合节点处理器,其通过从从LLR存储器读取的相应LLR值中减去所选择的校验节点的校验节点消息来生成变量节点消息,对变量节点消息执行校验节点处理,计算LLR 通过将变量节点消息添加到校验节点处理结果值来更新值,并将计算出的LLR值传递给LLR存储器。
    • 7. 发明申请
    • Method and apparatus for decoding low density parity check code using united node processing
    • 使用联合节点处理解码低密度奇偶校验码的方法和装置
    • US20060123318A1
    • 2006-06-08
    • US11283732
    • 2005-11-22
    • Sang-Hyo KimSung-Jin ParkHan-Ju KimMin-Goo Kim
    • Sang-Hyo KimSung-Jin ParkHan-Ju KimMin-Goo Kim
    • H03M13/00
    • H03M13/1137H03M13/1114H03M13/114H03M13/116
    • A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.
    • 提供了一种解码包括多个校验节点和多个可变节点的LDPC码的方法和装置。 该装置包括校验节点选择调度器,该校验节点选择调度器选择校验节点中的至少一个,将可变节点的输入LLR值存储为初始LLR值的LLR存储器,并且存储用于连接到所选校验节点的变量节点的更新的LLR值 以及检查节点消息存储器,其将选择的校验节点上指示校验节点处理的结果值的校验节点消息存储。 该装置还包括至少一个联合节点处理器,其通过从从LLR存储器读取的相应LLR值中减去所选择的校验节点的校验节点消息来生成变量节点消息,对变量节点消息执行校验节点处理,计算LLR 通过将变量节点消息添加到校验节点处理结果值来更新值,并将计算出的LLR值传递给LLR存储器。