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1. 发明申请

US20110254081A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110254081A1
公开(公告)日：2011-10-20
申请号：US13168301
申请日：2011-06-24
申请人： Sang-Hoon CHO , Yun-Seok CHO , Myung-Ok KIM , Sang-Hoon PARK , Young-Kyun JUNG
发明人： Sang-Hoon CHO , Yun-Seok CHO , Myung-Ok KIM , Sang-Hoon PARK , Young-Kyun JUNG
IPC分类号： H01L29/78
CPC分类号： H01L21/823487 , H01L29/66666
摘要： In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
摘要翻译：在一种在包括多个柱状图案的基板上制造半导体器件的方法中，相邻柱状图案之间的杂质区域，每个柱状图案上的栅极电极，覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层，形成覆盖栅电极的牺牲层，在每个柱状图案的侧壁上形成第二覆盖层，去除牺牲层，并且形成连接相邻柱状图案的栅电极的字线。在所制造的器件中，第一覆盖层将杂质区域与字线隔离，并且第二封盖区域防止相应柱状图案的侧壁暴露。

2. 发明申请

US20090242971A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090242971A1
公开(公告)日：2009-10-01
申请号：US12334324
申请日：2008-12-12
申请人： Sang-Hoon CHO , Yun-Seok CHO , Myung-Ok KIM , Sang-Hoon PARK , Young-Kyun JUNG
发明人： Sang-Hoon CHO , Yun-Seok CHO , Myung-Ok KIM , Sang-Hoon PARK , Young-Kyun JUNG
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823487 , H01L29/66666
摘要： In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
摘要翻译：在一种在包括多个柱状图案的基板上制造半导体器件的方法中，相邻柱状图案之间的杂质区域，每个柱状图案上的栅极电极，覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层，形成覆盖栅电极的牺牲层，在每个柱状图案的侧壁上形成第二覆盖层，去除牺牲层，并且形成连接相邻柱状图案的栅电极的字线。在所制造的器件中，第一覆盖层将杂质区域与字线隔离，并且第二封盖区域防止相应柱状图案的侧壁暴露。

3. 发明申请

US20080176402A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH RECESS GATE 审中-公开
标题翻译：用于制造具有压盖的半导体器件的方法
公开(公告)号：US20080176402A1
公开(公告)日：2008-07-24
申请号：US11968446
申请日：2008-01-02
申请人： Myung-Ok KIM , Tae-Woo JUNG
发明人： Myung-Ok KIM , Tae-Woo JUNG
IPC分类号： H01L21/311
CPC分类号： H01L21/31122 , H01L21/3065 , H01L21/3081 , H01L21/3083 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes providing a substrate, forming a sacrificial oxide layer over the substrate, the sacrificial layer having a higher etch rate than the substrate, forming a hard mask pattern over the sacrificial oxide layer, wet-etching the sacrificial oxide layer using the hard mask pattern as an etch barrier, and forming a recess by etching an exposed substrate using the hard mask pattern as an etch barrier.
摘要翻译：一种用于制造半导体器件的方法包括提供衬底，在衬底上形成牺牲氧化物层，牺牲层具有比衬底更高的蚀刻速率，在牺牲氧化物层上形成硬掩模图案，湿蚀刻牺牲氧化物使用硬掩模图案作为蚀刻阻挡层，以及通过使用硬掩模图案作为蚀刻阻挡层蚀刻暴露的基板来形成凹部。

4. 发明申请

US20090045465A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090045465A1
公开(公告)日：2009-02-19
申请号：US12165129
申请日：2008-06-30
申请人： Myung-Ok KIM
发明人： Myung-Ok KIM
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/76897 , H01L21/823475 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the recess pattern so that only a gate hard mask layer is exposed above a substrate surface. Since the gate electrode is not exposed above the substrate, it is possible to prevent SAC failure and decrease an aspect ratio of a gate pattern to increase an open margin of a contact hole. Thus, a semiconductor device having a recess channel gate structure which exhibits a superior refresh property is fabricated.
摘要翻译：半导体器件可以防止由掩模之间的未对准引起的凹部图案的内壁的暴露。在凹槽图案内部形成栅电极，使得仅在栅极表面露出栅极硬掩模层。由于栅极没有暴露在基板上方，因此可以防止SAC故障并且减小栅极图案的纵横比以增加接触孔的开口边缘。因此，制造具有优异刷新特性的具有凹槽通道栅极结构的半导体器件。

5. 发明申请

US20080160766A1 METHOD FOR FABRICATING BULB-SHAPED RECESS PATTERN 失效
标题翻译：用于制作BULB型收缩图案的方法
公开(公告)号：US20080160766A1
公开(公告)日：2008-07-03
申请号：US11748617
申请日：2007-05-15
申请人： Myung-Ok KIM , Tae-Hyoung KIM
发明人： Myung-Ok KIM , Tae-Hyoung KIM
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/3065 , H01L21/31116 , H01L21/31122 , H01L29/4236 , H01L29/66621
摘要： A method for fabricating a bulb-shaped recess pattern includes: forming an etch barrier layer over a substrate; forming a hard mask pattern in which a first polymer is attached to sidewalls of the hard mask pattern over the etch barrier layer; sequentially etching the etch barrier layer and the substrate to form a recess pattern in which a second polymer is attached to sidewalls of the recess pattern; removing the first and second polymers and the hard mask pattern; forming a plurality of spacers exposing a bottom portion of the recess pattern; and etching the exposed bottom portion of the recess pattern to form a ball pattern.
摘要翻译：一种用于制造球形凹槽图案的方法包括：在衬底上形成蚀刻阻挡层; 形成硬掩模图案，其中第一聚合物附着在蚀刻阻挡层上的硬掩模图案的侧壁上; 依次蚀刻蚀刻阻挡层和基底以形成其中第二聚合物附着到凹槽图案的侧壁上的凹陷图案; 去除第一和第二聚合物和硬掩模图案; 形成暴露所述凹部图形的底部的多个间隔件; 并且蚀刻凹陷图案的暴露的底部部分以形成球形图案。

6. 发明申请

US20080132074A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH RECESS GATE 有权
标题翻译：用于制造具有压盖的半导体器件的方法
公开(公告)号：US20080132074A1
公开(公告)日：2008-06-05
申请号：US11931510
申请日：2007-10-31
申请人： Myung-Ok KIM
发明人： Myung-Ok KIM
IPC分类号： H01L21/311
CPC分类号： H01L29/66553 , H01L27/10876 , H01L29/1037 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes forming a first recess in a substrate, forming a plasma oxide layer over the substrate including first recess, etching the plasma oxide layer to have a portion of the plasma oxide layer remain on sidewalls of the first recess, and forming a second recess by isotropically etching a bottom portion of the first recess, wherein the second recess has a width greater than a width of the first recess.
摘要翻译：一种制造半导体器件的方法包括在衬底中形成第一凹槽，在包括第一凹槽的衬底上形成等离子体氧化物层，蚀刻等离子体氧化物层以使等离子体氧化物层的一部分保留在第一凹槽的侧壁上，以及通过各向同性蚀刻所述第一凹部的底部而形成第二凹部，其中所述第二凹部的宽度大于所述第一凹部的宽度。

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