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1. 发明申请

US20130163345A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20130163345A1
公开(公告)日：2013-06-27
申请号：US13605552
申请日：2012-09-06
申请人： Sang Tae AHN , Gyu Seog Cho , Chae Moon Lim , Yoo Nam Jeon , Seung Hwan Baik , Hee Jin Lee , Jae Seok Kim , Kyung Sik Mun , U Seon Im
发明人： Sang Tae AHN , Gyu Seog Cho , Chae Moon Lim , Yoo Nam Jeon , Seung Hwan Baik , Hee Jin Lee , Jae Seok Kim , Kyung Sik Mun , U Seon Im
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3427
摘要： A method of operating a semiconductor memory device includes an operation of applying a first voltage to selected bit lines, a second voltage to unselected bit lines and a common source line, and turning on drain and source selection transistors, an operation of applying a program voltage to a selected word line and a switch voltage to a switch word line, and applying a first pass voltage to first unselected word lines disposed between the switch word line and a common source line and between the selected word line and a bit line, and elevating the switch voltage to generate hot electrons and inject the hot electrons to a selected memory cell of the selected word line to program the selected cell.
摘要翻译：一种操作半导体存储器件的方法包括：将第一电压施加到所选择的位线，将第二电压施加到未选定位线和公共源极线，以及接通漏极和源极选择晶体管的操作，施加编程电压将选择的字线和开关电压切换到开关字线，并且将第一通过电压施加到设置在开关字线和公共源极线之间以及所选择的字线和位线之间的第一未选择字线，并且升高所述开关电压产生热电子并将热电子注入到所选择的字线的选定的存储单元中以对所选择的单元进行编程。

2. 发明授权

US08937348B2 3-D nonvolatile memory device, memory system, and manufacturing method thereof 有权
标题翻译： 3-D非易失性存储器件，存储器系统及其制造方法
公开(公告)号：US08937348B2
公开(公告)日：2015-01-20
申请号：US13601641
申请日：2012-08-31
申请人： Yoo Nam Jeon
发明人： Yoo Nam Jeon
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/11582 , H01L29/7926
摘要： A three dimensional (3-D) nonvolatile memory device includes a first pipe gate layer, a second pipe gate disposed over the first pipe gate layer, word lines formed over the second pipe gate layer, memory channel layers configured to penetrate the word lines, a pipe channel layer formed in the first pipe gate layer, where the pipe channel layer is to come in contact with the bottom surface of the second pipe gate layer and couple the lower ends of the memory channel layers, a memory layer configured to surround the pipe channel layer and the memory channel layers, and a first gate insulating layer interposed between the first pipe gate layer and the memory layer.
摘要翻译：三维（3-D）非易失性存储器件包括第一管栅层，设置在第一管栅层上的第二管栅，形成在第二管栅层上的字线，被配置为穿透字线的存储通道层，形成在第一管栅层中的管道沟道层，其中管道沟道层将与第二管栅极层的底表面接触并耦合存储通道层的下端;存储层，被配置为围绕管道沟道层和存储通道层，以及插入在第一管栅极层和存储层之间的第一栅极绝缘层。

3. 发明授权

US07663912B2 Non-volatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07663912B2
公开(公告)日：2010-02-16
申请号：US11770685
申请日：2007-06-28
申请人： Yoo Nam Jeon
发明人： Yoo Nam Jeon
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device and a method of fabricating the same are disclosed. The method includes the steps of: providing a semiconductor substrate having isolation layers in an isolation region, a tunnel insulating layer formed between the isolation layers, and first electron charge layers formed between the isolation layers, wherein the isolation layers comprise projections extending higher than the semiconductor substrate; etching the first electron charge layers, thereby reducing the thickness of the first electron charge layers and exposing sidewalls of the isolation layers; performing a first etch process to reduce the width of the projections; forming second electron charge layers between the projections on the first electron charge layers; and performing a second etch process to remove the projections between the second electron charge layers.
摘要翻译：公开了一种非易失性存储器件及其制造方法。该方法包括以下步骤：提供在隔离区域中具有隔离层的半导体衬底，形成在隔离层之间的隧道绝缘层以及形成在隔离层之间的第一电子电荷层，其中隔离层包括高于半导体衬底; 蚀刻第一电子电荷层，从而减小第一电子电荷层的厚度并暴露隔离层的侧壁; 执行第一蚀刻工艺以减小突起的宽度; 在第一电子电荷层上的突起之间形成第二电子电荷层; 以及执行第二蚀刻工艺以去除第二电子电荷层之间的突起。

4. 发明申请

US20090227080A1 Method of Fabricating Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090227080A1
公开(公告)日：2009-09-10
申请号：US12399271
申请日：2009-03-06
申请人： Yoo Nam Jeon
发明人： Yoo Nam Jeon
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76877 , H01L23/485 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device, in which although a metal layer is included in a gate pattern, the gap-fill characteristic of contact plugs coupled to junctions can be improved and degradation in the data retention characteristic can also be prevented. According to the method, a semiconductor substrate in which lower gate patterns and gate hard mask patterns are sequentially stacked is first provided. Junctions are formed in the semiconductor substrate on both sides of each of the lower gate patterns. A first pre-metal dielectric layer is formed over the semiconductor substrate in which the hard mask patterns and the junctions are formed. Contact holes through which the junctions are exposed are formed in the first pre-metal dielectric layer. Gate trenches through which the lower gate patterns are exposed are formed by removing the hard mask patterns. Upper gate patterns, each including a metal layer, are formed in the gate trenches, and first contact plugs are formed in the contact holes.
摘要翻译：一种制造半导体器件的方法，其中虽然金属层包括在栅极图案中，但是可以提高耦合到结的接触插塞的间隙填充特性，并且还可以防止数据保持特性的劣化。根据该方法，首先提供顺序堆叠下部栅极图案和栅极硬掩模图案的半导体衬底。在每个下栅极图案的两侧的半导体衬底中形成接合部。在其上形成有硬掩模图案和结的半导体基板上形成第一预金属介电层。在第一预金属介电层中形成有接合孔暴露出的接触孔。通过去除硬掩模图案来形成通过其露出下部栅极图案的栅极沟槽。每个包括金属层的上部栅极图案形成在栅极沟槽中，并且第一接触插塞形成在接触孔中。

5. 发明授权

US08625359B2 Programming method of flash memory device 有权
标题翻译：闪存设备的编程方法
公开(公告)号：US08625359B2
公开(公告)日：2014-01-07
申请号：US12016805
申请日：2008-01-18
申请人： Yoo Nam Jeon , Keon Soo Shim
发明人： Yoo Nam Jeon , Keon Soo Shim
IPC分类号： G11C16/06 , G11C16/08 , G11C16/10 , G11C16/12
CPC分类号： G11C16/0483 , G11C16/10
摘要： A memory device comprises a drain select line, a source select line, word lines, and a string connected between a bit line and a common source line. A program-inhibited voltage is applied to the bit line and a first voltage of a positive potential is applied to the drain select line. A second voltage for activating a programmed memory cell is applied to a word line to which the programmed memory cell is connected. A programming operation is performed by applying a program voltage to a selected word line and applying a pass voltage to the unselected word lines.
摘要翻译：存储器件包括漏极选择线，源选择线，字线和连接在位线和公共源极线之间的串。向位线施加编程禁止电压，并且将正电位的第一电压施加到漏极选择线。用于激活编程的存储器单元的第二电压被施加到被编程的存储器单元连接到的字线。通过向所选择的字线施加编程电压并对未选择的字线施加通过电压来执行编程操作。

6. 发明授权

US07855921B2 Erase method and soft programming method of non-volatile memory device 失效
标题翻译：非易失性存储器件的擦除方法和软编程方法
公开(公告)号：US07855921B2
公开(公告)日：2010-12-21
申请号：US12131962
申请日：2008-06-03
申请人： Yoo Nam Jeon
发明人： Yoo Nam Jeon
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： An erase method and a soft programming method of a non-volatile memory device includes performing an erase operation on a memory cell block; applying a pass voltage to a memory cell adjacent to a select transistor of the memory cell block; applying a soft program voltage to the remaining memory cells of the memory cell block; and performing a soft program operation.
摘要翻译：非易失性存储器件的擦除方法和软编程方法包括对存储器单元块进行擦除操作; 对与存储单元块的选择晶体管相邻的存储单元施加通过电压; 将软编程电压施加到存储器单元块的剩余存储单元; 并执行软程序操作。

7. 发明授权

US07410881B2 Method of manufacturing flash memory device 失效
标题翻译：制造闪存设备的方法
公开(公告)号：US07410881B2
公开(公告)日：2008-08-12
申请号：US11618702
申请日：2006-12-29
申请人： Sun Mi Park , Yoo Nam Jeon , Nam Kyeong Kim , Se Jun Kim
发明人： Sun Mi Park , Yoo Nam Jeon , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L21/76849 , H01L21/76877 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive material, the first conductive material contacting the junction region and extending above an upper surface of the contact hole. The first conductive material is etched to partly fill the contact hole, so that the first conductive material fills a lower portion of the contact hole, wherein an upper portion of the contact hole remains not filled due to the etching of the first conductive material, wherein the etched first conductive material defines a contact plug. A first dielectric layer and a second dielectric layer are formed over the contact plug, thereby filling the upper portion of the contact hole. Part of the first and second dielectric layers is etched to expose the contact plug and the upper portion of the contact hole. A second conductive material is formed on the contact plug and filling the upper portion of the contact hole to form a bit line.
摘要翻译：制造闪速存储器件的方法包括蚀刻设置在衬底上的绝缘层以形成接触孔，以限定暴露形成在衬底上的接合区域的接触孔。接触孔填充有第一导电材料，第一导电材料接触接合区并在接触孔的上表面上方延伸。第一导电材料被蚀刻以部分地填充接触孔，使得第一导电材料填充接触孔的下部，其中接触孔的上部部分由于蚀刻第一导电材料而保持不被填充，其中蚀刻的第一导电材料限定接触插塞。第一电介质层和第二电介质层形成在接触插塞上，从而填充接触孔的上部。蚀刻第一和第二电介质层的一部分以暴露接触插塞和接触孔的上部。第二导电材料形成在接触插塞上并填充接触孔的上部以形成位线。

8. 发明授权

US07933149B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07933149B2
公开(公告)日：2011-04-26
申请号：US12650484
申请日：2009-12-30
申请人： Yoo Nam Jeon
发明人： Yoo Nam Jeon
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device and a method of fabricating the same are disclosed. The method includes the steps of: providing a semiconductor substrate having isolation layers in an isolation region, a tunnel insulating layer formed between the isolation layers, and first electron charge layers formed between the isolation layers, wherein the isolation layers comprise projections extending higher than the semiconductor substrate; etching the first electron charge layers, thereby reducing the thickness of the first electron charge layers and exposing sidewalls of the isolation layers; performing a first etch process to reduce the width of the projections; forming second electron charge layers between the projections on the first electron charge layers; and performing a second etch process to remove the projections between the second electron charge layers.
摘要翻译：公开了一种非易失性存储器件及其制造方法。该方法包括以下步骤：提供在隔离区域中具有隔离层的半导体衬底，形成在隔离层之间的隧道绝缘层以及形成在隔离层之间的第一电子电荷层，其中隔离层包括高于半导体衬底; 蚀刻第一电子电荷层，从而减小第一电子电荷层的厚度并暴露隔离层的侧壁; 执行第一蚀刻工艺以减小突起的宽度; 在第一电子电荷层上的突起之间形成第二电子电荷层; 以及执行第二蚀刻工艺以去除第二电子电荷层之间的突起。

9. 发明授权

US07851290B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07851290B2
公开(公告)日：2010-12-14
申请号：US12399271
申请日：2009-03-06
申请人： Yoo Nam Jeon
发明人： Yoo Nam Jeon
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/20 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76877 , H01L23/485 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device, in which although a metal layer is included in a gate pattern, the gap-fill characteristic of contact plugs coupled to junctions can be improved and degradation in the data retention characteristic can also be prevented. According to the method, a semiconductor substrate in which lower gate patterns and gate hard mask patterns are sequentially stacked is first provided. Junctions are formed in the semiconductor substrate on both sides of each of the lower gate patterns. A first pre-metal dielectric layer is formed over the semiconductor substrate in which the hard mask patterns and the junctions are formed. Contact holes through which the junctions are exposed are formed in the first pre-metal dielectric layer. Gate trenches through which the lower gate patterns are exposed are formed by removing the hard mask patterns. Upper gate patterns, each including a metal layer, are formed in the gate trenches, and first contact plugs are formed in the contact holes.
摘要翻译：一种制造半导体器件的方法，其中虽然金属层包括在栅极图案中，但是可以提高耦合到结的接触插塞的间隙填充特性，并且还可以防止数据保持特性的劣化。根据该方法，首先提供顺序堆叠下部栅极图案和栅极硬掩模图案的半导体衬底。在每个下栅极图案的两侧的半导体衬底中形成接合部。在其上形成有硬掩模图案和结的半导体基板上形成第一预金属介电层。在第一预金属介电层中形成有接合孔暴露出的接触孔。通过去除硬掩模图案来形成通过其露出下部栅极图案的栅极沟槽。每个包括金属层的上部栅极图案形成在栅极沟槽中，并且第一接触插塞形成在接触孔中。

10. 发明申请

US20100178745A1 Flash Memory Device and Fabrication Method Thereof 有权
标题翻译：闪存设备及其制作方法
公开(公告)号：US20100178745A1
公开(公告)日：2010-07-15
申请号：US12731594
申请日：2010-03-25
申请人： Yoo Nam Jeon , Ki Seog Kim
发明人： Yoo Nam Jeon , Ki Seog Kim
IPC分类号： H01L21/336
CPC分类号： G11C16/0483 , G11C16/3418 , G11C16/3427 , H01L27/11521 , H01L27/11524
摘要： The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence of a program disturbance phenomenon can be prevented as the injection of hot carriers into a program-inhibited cell is minimized in a program operation.
摘要翻译：本发明涉及闪速存储器件及其制造方法。可以在字线之间的接合区域中形成沟槽，通过不仅在字线和选择线之间，而且在相邻字线之间蚀刻半导体衬底。因此，由于在程序操作中将热载流子注入到程序禁止单元中被最小化，所以可以防止编程干扰现象的发生。

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