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1. 发明申请

US20160071594A1 Non-Volatile Memory with Multi-Word Line Select for Defect Detection Operations 有权
标题翻译：具有多字线选择的非易失性存储器用于缺陷检测操作
公开(公告)号：US20160071594A1
公开(公告)日：2016-03-10
申请号：US14477339
申请日：2014-09-04
申请人： SanDisk Technologies Inc.
发明人： Rajan Paudel , Jagdish Sabde , Sagar Magia , Khanh Nguyen
IPC分类号： G11C16/10 , G11C16/08 , G11C16/04
CPC分类号： G11C16/10 , G11C8/14 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C29/26 , G11C2029/1202 , G11C2029/2602
摘要： A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.
摘要翻译：描述了用于测试用于多种类型的缺陷的非易失性存储器阵列的应力模式。更具体地，对于给定块的多字线选择选项可以用于要设置为编程或其它高电压的一组选定字线，而块的未选字线被设置为通过电压以尽量减少电场差异，以避免干扰。例如，一组选定的字线可以编号为4,8或16.多字线选项可以应用于每个平面的一个块，使得如果存在两个存储器平面，则可以选择两个这样的块同时为这些块的多字行选项。

2. 发明授权

US09449694B2 Non-volatile memory with multi-word line select for defect detection operations 有权
标题翻译：具有多字线选择的非易失性存储器用于缺陷检测操作
公开(公告)号：US09449694B2
公开(公告)日：2016-09-20
申请号：US14477339
申请日：2014-09-04
申请人： SanDisk Technologies Inc.
发明人： Rajan Paudel , Jagdish Sabde , Sagar Magia , Khanh Nguyen
IPC分类号： G11C16/10 , G11C16/08 , G11C8/14 , G11C11/56 , G11C29/26 , G11C16/04 , G11C29/12
CPC分类号： G11C16/10 , G11C8/14 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C29/26 , G11C2029/1202 , G11C2029/2602
摘要： A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.
摘要翻译：描述了用于测试用于多种类型的缺陷的非易失性存储器阵列的应力模式。更具体地，对于给定块的多字线选择选项可以用于要设置为编程或其它高电压的一组选定字线，而块的未选字线被设置为通过电压以尽量减少电场差异，以避免干扰。例如，一组选定的字线可以编号为4,8或16.多字线选项可以应用于每个平面的一个块，使得如果存在两个存储器平面，则可以选择两个这样的块同时为这些块的多字行选项。

3. 发明申请

US20160260495A1 Word Line Look Ahead Read For Word Line To Word Line Short Detection 有权
标题翻译：字线前瞻阅读字线到字线短检测
公开(公告)号：US20160260495A1
公开(公告)日：2016-09-08
申请号：US14919472
申请日：2015-10-21
申请人： SanDisk Technologies Inc.
发明人： Rajan Paudel , Jagdish Sabde , Mrinal Kochar , Sagar Magia
IPC分类号： G11C16/34 , G11C16/26 , G11C29/50 , G11C16/16
CPC分类号： G11C16/3427 , G11C16/16 , G11C16/26 , G11C16/3431 , G11C16/3445 , G11C29/025 , G11C29/44 , G11C29/50 , G11C2029/1202
摘要： Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.
摘要翻译：提供了用于操作检测字线短路（例如相邻字线之间的短路）的存储器件的技术。在示例实现中，在编程操作期间，计数用于完成编程或到达WLn的另一编程里程碑的程序循环的数量。如果程序循环数超过循环计数限制，则评估WLn + 1的存储单元以确定是否存在短路。评估涉及对WLn + 1的Vth分布的上尾部中的擦除状态存储单元进行计数的读取操作。如果计数超过位计数限制，则可以断定WLn和WLn + 1之间出现短路，并采取纠正措施。循环计数限制随着编程擦除周期数的增加而调低。

4. 发明授权

US09548129B2 Word line look ahead read for word line to word line short detection 有权
标题翻译：字线前瞻阅读字线到字线短路检测
公开(公告)号：US09548129B2
公开(公告)日：2017-01-17
申请号：US14919472
申请日：2015-10-21
申请人： SanDisk Technologies Inc.
发明人： Rajan Paudel , Jagdish Sabde , Mrinal Kochar , Sagar Magia
IPC分类号： G11C11/34 , G11C16/34 , G11C16/16 , G11C16/26 , G11C29/50
CPC分类号： G11C16/3427 , G11C16/16 , G11C16/26 , G11C16/3431 , G11C16/3445 , G11C29/025 , G11C29/44 , G11C29/50 , G11C2029/1202
摘要： Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.
摘要翻译：提供了用于操作检测字线短路（例如相邻字线之间的短路）的存储器件的技术。在示例实现中，在编程操作期间，计数用于完成编程或到达WLn的另一编程里程碑的程序循环的数量。如果程序循环数超过循环计数限制，则评估WLn + 1的存储单元以确定是否存在短路。评估涉及对WLn + 1的Vth分布的上尾部中的擦除状态存储单元进行计数的读取操作。如果计数超过位计数限制，则可以断定WLn和WLn + 1之间出现短路，并采取纠正措施。循环计数限制随着编程擦除周期数的增加而调低。

5. 发明授权

US09496040B2 Adaptive multi-page programming methods and apparatus for non-volatile memory 有权
标题翻译：用于非易失性存储器的自适应多页面编程方法和装置
公开(公告)号：US09496040B2
公开(公告)日：2016-11-15
申请号：US14602468
申请日：2015-01-22
申请人： SanDisk Technologies Inc.
发明人： Rajan Paudel , Jagdish Sabde , Sagar Magia
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5644
摘要： A method is provided for programming a memory cell connected to a selected word line in a memory device. The method includes performing one programming pass of a multi-pass programming operation for the memory cell, wherein a first set of program pulses is applied to the selected word line during the one programming pass, determining a number of the program pulses applied to the selected word line during the one programming pass, determining a difference between the determined number of program pulses applied to the selected word line during the one programming pass and a predetermined number of program pulses, adjusting a parameter of a second set of program pulses for the another programming pass based on the determined difference, and performing the another programming pass for the set of memory cells, wherein the second set of program pulses is applied to the selected word line during the another programming pass.
摘要翻译：提供了一种用于对连接到存储器件中所选字线的存储器单元进行编程的方法。该方法包括对存储单元执行多遍编程操作的一个编程遍历，其中在一个编程遍期间将第一组编程脉冲施加到所选择的字线，确定施加到所选择的编程脉冲的数量在一个编程通过期间，确定在一个编程遍期间施加到所选择的字线的所确定的编程脉冲数与预定数量的编程脉冲之间的差异，调整另一个编程脉冲的第二组编程脉冲的参数基于所确定的差异进行编程通过，以及对所述存储器单元组执行另一编程遍，其中所述第二组编程脉冲在另一编程遍期间被施加到所选择的字线。

6. 发明申请

US20160217857A1 ADAPTIVE MULTI-PAGE PROGRAMMING METHODS AND APPARATUS FOR NON-VOLATILE MEMORY 有权
标题翻译：自适应多媒体编程方法和非易失性存储器的设备
公开(公告)号：US20160217857A1
公开(公告)日：2016-07-28
申请号：US14602468
申请日：2015-01-22
申请人： SanDisk Technologies Inc.
发明人： Rajan Paudel , Jagdish Sabde , Sagar Magia
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5644
摘要： A method is provided for programming a memory cell connected to a selected word line in a memory device. The method includes performing one programming pass of a multi-pass programming operation for the memory cell, wherein a first set of program pulses is applied to the selected word line during the one programming pass, determining a number of the program pulses applied to the selected word line during the one programming pass, determining a difference between the determined number of program pulses applied to the selected word line during the one programming pass and a predetermined number of program pulses, adjusting a parameter of a second set of program pulses for the another programming pass based on the determined difference, and performing the another programming pass for the set of memory cells, wherein the second set of program pulses is applied to the selected word line during the another programming pass.
摘要翻译：提供了一种用于对连接到存储器件中所选字线的存储器单元进行编程的方法。该方法包括对存储单元执行多遍编程操作的一个编程遍历，其中在一个编程遍期间将第一组编程脉冲施加到所选择的字线，确定施加到所选择的编程脉冲的数量在一个编程通过期间，确定在一个编程遍期间施加到所选择的字线的所确定的编程脉冲数与预定数量的编程脉冲之间的差异，调整另一个编程脉冲的第二组编程脉冲的参数基于所确定的差异进行编程通过，以及对所述存储器单元组执行另一编程遍，其中所述第二组编程脉冲在另一编程遍期间被施加到所选择的字线。

7. 发明授权

US09449698B1 Block and zone erase algorithm for memory 有权
标题翻译：用于存储器的块和区域擦除算法
公开(公告)号：US09449698B1
公开(公告)日：2016-09-20
申请号：US14887976
申请日：2015-10-20
申请人： SanDisk Technologies Inc.
发明人： Rajan Paudel , Jagdish Sabde , Sagar Magia
IPC分类号： G11C16/04 , G11C16/14 , G11C16/34
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/3436 , G11C16/3445 , G11C16/3495
摘要： Techniques are provided for erasing a memory device. In one aspect, different zones of a block can be separately erased and subject to a verify test. Erase parameters can be optimized for each zone, so that endurance is improved. If one zone is found to be too slow to erase, it can be marked as being bad while other zones remain available for use. In another aspect, the zone-based erase occurs after a block based erased when a criterion is met, such as the block-based erase being too slow or failing to complete within an allowable number of program loops. The zone-based erase can occur after the block-based erase in the same erase operation, or in a subsequent, new erase operation.
摘要翻译：提供了用于擦除存储器件的技术。在一个方面，块的不同区域可以被单独地擦除并进行验证测试。可以为每个区域优化擦除参数，从而提高耐久性。如果发现一个区域太慢而无法擦除，则可能会将其标记为坏，而其他区域仍可供使用。在另一方面，当基于块的擦除被符合标准时，例如基于块的擦除太慢或在允许的程序循环数量内完成，基于区块擦除发生。基于区域的擦除可以在相同的擦除操作或随后的新的擦除操作中的基于块的擦除之后发生。

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