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1. 发明授权

US07930610B2 System and method for power reduction through power aware latch weighting of complex sub-circuits 有权
标题翻译：通过复杂子电路的功率感知锁存器加权降低功耗的系统和方法
公开(公告)号：US07930610B2
公开(公告)日：2011-04-19
申请号：US12206781
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。

2. 发明授权

US07925948B2 System and method for power reduction through power aware latch weighting 有权
标题翻译：通过功率感知锁存器加权降低功耗的系统和方法
公开(公告)号：US07925948B2
公开(公告)日：2011-04-12
申请号：US12206789
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
IPC分类号： G01R31/28
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位模式。电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。

3. 发明申请

US20100064190A1 System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits 有权
标题翻译：通过电力方面的功率降低系统和方法，复杂子电路的锁存加权
公开(公告)号：US20100064190A1
公开(公告)日：2010-03-11
申请号：US12206781
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。

4. 发明申请

US20100064189A1 System and Method for Power Reduction Through Power Aware Latch Weighting 有权
标题翻译：通过电源意识锁定加权降低功耗的系统和方法
公开(公告)号：US20100064189A1
公开(公告)日：2010-03-11
申请号：US12206789
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
IPC分类号： G06F11/00
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位模式。电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。

5. 发明申请

US20090254788A1 Techniques for Logic Built-In Self-Test Diagnostics of Integrated Circuit Devices 有权
标题翻译：逻辑内置自检诊断技术集成电路器件
公开(公告)号：US20090254788A1
公开(公告)日：2009-10-08
申请号：US12061752
申请日：2008-04-03
申请人： Daniel W. Cervantes , Robert B. Gass , Joshua P. Hernandez , Timothy M. Skergan
发明人： Daniel W. Cervantes , Robert B. Gass , Joshua P. Hernandez , Timothy M. Skergan
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/3187 , G11C29/12015 , G11C29/16 , G11C29/44 , G11C2029/0405 , G11C2029/3202
摘要： A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., “signature” of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.
摘要翻译：一种用于执行IC器件实时LBIST诊断的方法，系统和计算机程序产品。在LBIST期间，残留数据和测试周期的标识符保存在IC器件中（DUT）中。如果压缩树桩数据与预定义的编码值（即测试周期的“签名”）不匹配，则保存的桩号数据和故障测试周期的标识符被保留，否则确定DUT通过测试周期。故障测试周期的标识符和残差用于分析错误，包括几乎不可重现的错误。

6. 发明授权

US07519889B1 System and method to reduce LBIST manufacturing test time of integrated circuits 失效
标题翻译：减少LBIST制造测试时间集成电路的系统和方法
公开(公告)号：US07519889B1
公开(公告)日：2009-04-14
申请号：US12060339
申请日：2008-04-01
申请人： Daniel W. Cervantes , Joshua P. Hernandez , Tung N. Pham , Timothy M. Skergan
发明人： Daniel W. Cervantes , Joshua P. Hernandez , Tung N. Pham , Timothy M. Skergan
IPC分类号： G01R31/28
CPC分类号： G01R31/318385
摘要： A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.
摘要翻译：一种减少集成电路的自检制造测试时间内置逻辑的方法，其特征在于包括：将大量测试种子加载到本地可访问的本地设置在集成电路上的片上存储器阵列中，与一组LBIST控制信息相关联; 在LBIST控制信息的集合控制下的LBIST操作期间，一次一个地将多个测试种子从本地可访问的片上存储器阵列发送到伪随机模式生成器中; 通过使用多个测试种子将随机比特流串行地生成到集成电路的多个并行移位寄存器中; 以及对所述集成电路中的多个逻辑块执行逻辑内置自检以检测所述集成电路内的缺陷。

7. 发明授权

US07856582B2 Techniques for logic built-in self-test diagnostics of integrated circuit devices 有权
标题翻译：逻辑内置自检诊断技术的集成电路设备
公开(公告)号：US07856582B2
公开(公告)日：2010-12-21
申请号：US12061752
申请日：2008-04-03
申请人： Daniel W. Cervantes , Robert B. Gass , Joshua P. Hernandez , Timothy M. Skergan
发明人： Daniel W. Cervantes , Robert B. Gass , Joshua P. Hernandez , Timothy M. Skergan
IPC分类号： G01R31/28 , G01R31/02 , G01R31/26
CPC分类号： G01R31/318335 , G01R31/3187 , G11C29/12015 , G11C29/16 , G11C29/44 , G11C2029/0405 , G11C2029/3202
摘要： A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., “signature” of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.
摘要翻译：一种用于执行IC器件实时LBIST诊断的方法，系统和计算机程序产品。在LBIST期间，残留数据和测试周期的标识符保存在IC器件中（DUT）中。如果压缩树桩数据与预定义的编码值（即测试周期的“签名”）不匹配，则保存的桩号数据和故障测试周期的标识符被保留，否则确定DUT通过测试周期。故障测试周期的标识符和残差用于分析错误，包括几乎不可重现的错误。

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