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1. 发明授权

US5084913A Programmable multi-mode two-channel timing generator 失效
标题翻译：可编程多模双通道定时发生器
公开(公告)号：US5084913A
公开(公告)日：1992-01-28
申请号：US559011
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： H04B1/707
CPC分类号： H04B1/707
摘要： A novel universal multi-mode programmable two-channel timing generator employs a plurality of counters and logic circuitry. An input chip counter is coupled for receiving system clock signals and producing chip strobe and other output timing signals which are programmably capable of generating different rates of operation and different data or PN rates on different channels as well as different I and O enable signals for dedicated tracking and timing signals. The signals produced are used for synchronous-sample or non-synchronous-sample operation in a simple fast acting circuit designed for VLSI implementation.
摘要翻译：一种新型通用多模可编程双通道定时发生器采用多个计数器和逻辑电路。输入芯片计数器被耦合用于接收系统时钟信号并产生芯片选通和其他输出定时信号，其可编程地能够产生不同的操作速率和不同信道上的不同数据或PN速率，以及用于专用的不同的I和O使能信号跟踪和定时信号。所产生的信号用于设计用于VLSI实现的简单快速电路中的同步采样或非同步采样操作。

2. 发明授权

US5062071A Programmable gain accumulator 失效
标题翻译：可编程增益累加器
公开(公告)号：US5062071A
公开(公告)日：1991-10-29
申请号：US559019
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： G06F7/62
CPC分类号： G06F7/62
摘要： A programmable digital gain accumulator is provided with a digital accumulator having approximately the same number of significant bits as the input data stream. The most significant bit of the input data stream is a sign bit coupled to a series cascade of flip-flops providing a selectable plurality of flip-flop delay times. The carry output of the accumulator is coupled to an input up/down counter having its output coupled to a multiplexor capable of selecting one of the carry outputs of the input up/down counter. The up or down count is controlled by the sign bit input from the sign bit delay circuit. The output of the multiplexor is inputted to an output up/down counter whose parallel output is the parallel synchronous digital gain command signal for direct use by a utilization device. The up or down count of the output up/down counter is controlled by a delayed sign input from the sign bit delay circuit.
摘要翻译：可编程数字增益累加器具有与输入数据流大致相同数量的有效位的数字累加器。输入数据流的最高有效位是耦合到提供可选择的多个触发器延迟时间的触发器的串联级联的符号位。累加器的进位输出耦合到输入上/下计数器，其输出耦合到能够选择输入上/下计数器的进位输出中的一个的多路复用器。向上或向下计数由符号位延迟电路输入的符号位控制。多路复用器的输出被输入到并行输出是并行同步数字增益命令信号的输出上/下计数器，供直接由利用装置使用。输出上/下计数器的向上或向下计数由来自符号位延迟电路的延迟符号输入控制。

3. 发明授权

US5060180A Programmable digital loop filter 失效
标题翻译：可编程数字环路滤波器
公开(公告)号：US5060180A
公开(公告)日：1991-10-22
申请号：US559014
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： H03H17/02 , H04B1/7085
CPC分类号： H04B1/7085 , H03H17/0294
摘要： A programmable second order loop filter is provided with first and second programmable scaling circuits arranged in parallel and having their outputs connected to first and second programmable one bit serial adders respectively. The output of the second programmable serial adder is coupled to the input of said first programmable serial adder and has its output coupled to the input of a programmable output stage so as to provide the ability to maintain the average quantization bit error to one-half of one bit of the least significant bit of the full loop filter width even though the output does not use or employ all of the significant bits.
摘要翻译：可编程二阶环路滤波器被提供有并联布置的第一和第二可编程缩放电路，并且其输出分别连接到第一和第二可编程一位串行加法器。第二可编程串行加法器的输出耦合到所述第一可编程串行加法器的输入，并且其输出耦合到可编程输出级的输入端，以便提供维持平均量化比特误差的一半的能力即使输出不使用或使用所有有效位，全环路滤波器宽度的最低有效位的一位也是。

4. 发明授权

US5134631A Digital gain controller 失效
标题翻译：数字增益控制器
公开(公告)号：US5134631A
公开(公告)日：1992-07-28
申请号：US559018
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： H03G3/20 , H04K3/00
CPC分类号： H03G3/3052 , H04K3/224
摘要： A novel programmable digital gain controller is provided for the automatic gain control loop of a communications receiver. The digital gain controller comprises a pair of digital detectors coupled to the real and imaginary components of a data stream for providing digital data magnitude output signals which are coupled to an adder whose output is coupled to a first input of a comparator having a second input coupled to a predetermined reference level command. The output of the comparator generates a digital error signal which is coupled to the input of a programmable gain accumulator having a second input proportional gain command so as to provide at the output of the programmable gain accumulator a digital gain command which may be coupled to a variable gain controlled amplifier which is connected in the input data stream of the channel of a communications receiver to provide a predetermine amplifier output level.
摘要翻译：为通信接收机的自动增益控制环路提供了一种新颖的可编程数字增益控制器。数字增益控制器包括耦合到数据流的实部和虚部的一对数字检测器，用于提供数字数据幅度输出信号，耦合到加法器，其输出耦合到具有第二输入耦合的比较器的第一输入到预定的参考水平命令。比较器的输出产生数字误差信号，该数字误差信号耦合到具有第二输入比例增益指令的可编程增益累加器的输入端，以便在可编程增益累加器的输出处提供数字增益命令，该数字增益命令可耦合到可变增益控制放大器，其连接在通信接收机的信道的输入数据流中，以提供预定的放大器输出电平。

5. 发明授权

US5128958A Digital time error signal generator 失效
标题翻译：数字时间误差信号发生器
公开(公告)号：US5128958A
公开(公告)日：1992-07-07
申请号：US559015
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： H04B1/7085
CPC分类号： H04B1/7085
摘要： A time error signal generator of the type employed in symbol time tracking loops is provided with a pre-accumulate and scale circuit for receiving an input data stream which is applied to a digital early sample-late sample circuit for generation an error signal indicative of a time magnitude difference between the analog transition time of the data and the chip strobe time multiplied by the sign of the data. The output of the early sample-late sample circuit is applied to a second accumulate and scale circuit for generating an accumulated error signal which is applied to an inverter. The inverter is provided with a decision directed tracking input indicative of the sign of the data sample and is employed to invert the accumulated error signal when the sign of the analog data is negative. The output of the inverter provides a digital time error tracking signal which is adapted to be coupled to a clock generation circuit or clock synthesizer for generating the tracking loop system clock as well as other strobe timing signals.
摘要翻译：在符号时间跟踪环路中使用的类型的时间误差信号发生器设置有预积累和缩放电路，用于接收输入数据流，该输入数据流被应用于数字早期采样 - 后采样电路，用于产生指示数据的模拟转换时间与芯片选通时间之间的时间幅度差乘以数据的符号。早期采样后采样电路的输出被施加到第二累积和标尺电路，用于产生施加到逆变器的累积误差信号。反相器具有指示数据采样的符号的判定定向跟踪输入，并且当模拟数据的符号为负时被用于反转累积的误差信号。反相器的输出提供数字时间误差跟踪信号，该信号适于耦合到时钟发生电路或时钟合成器，用于产生跟踪环路系统时钟以及其它选通定时信号。

6. 发明授权

US5101370A Programmable digital accumulate and scale circuit 失效
标题翻译：可编程数字累积和缩放电路
公开(公告)号：US5101370A
公开(公告)日：1992-03-31
申请号：US559017
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： G06F7/50 , G06F7/509
CPC分类号： G06F7/509
摘要： A novel accumulate and scale circuit is provided with an input accumulator which is only as wide as the input data stream. Additional most significant bits are generated to extend the output of the accumulate and scale circuit by providing and an up and down counter having a number of most significant bit stages. The adder stages of the input accumulator have their carry and borrow outputs coupled to the up and down counter for generating additional most significant bits.
摘要翻译：一个新颖的累积和缩放电路提供有一个输入累加器，它只有输入数据流一样宽。产生额外的最高有效位以通过提供具有多个最高有效位级的升降计数器来扩展累积和比例电路的输出。输入累加器的加法器级具有与进位和递减计数器相连的进位和借位输出，用于产生额外的最高有效位。

7. 发明授权

US5105437A Programmable digital acquisition and tracking controller 失效
标题翻译：可编程数字采集跟踪控制器
公开(公告)号：US5105437A
公开(公告)日：1992-04-14
申请号：US559013
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： H04B1/7075 , H04B1/7085
CPC分类号： H04B1/7075 , H04B1/7085
摘要： A novel programmable digital acquisition and tracking controller is coupled to the input signal level from the demodulator of a communications receiver and provides programmable signal level threshold detectors and detection intervals adapted to produce an output signal which is indicative of the correlation between the received PN code and the locally generated PN code as compared against a programmable threshold. The programmable detector logic is capable of detecting acquisition correlation and tracking correlation and can optionally inform an external microprocessor of the correlation level so as to implement a wide variety of acquisition, tracking and reacquisition algorithms as well as optional AM demodulation.
摘要翻译：一种新颖的可编程数字采集和跟踪控制器被耦合到来自通信接收机的解调器的输入信号电平，并且提供可编程信号电平门限检测器和检测间隔，其适于产生输出信号，该输出信号指示所接收的PN码与本地产生的PN码与可编程阈值相比。可编程检测器逻辑能够检测采集相关和跟踪相关性，并且可以可选地向外部微处理器通知相关级，以便实现各种采集，跟踪和重新获取算法以及可选的AM解调。

8. 发明授权

US5099494A Six channel digital demodulator 失效
标题翻译：六通道DIGITAL DEMODULATOR
公开(公告)号：US5099494A
公开(公告)日：1992-03-24
申请号：US559012
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： H04B1/66 , H04B1/707 , H04L27/00 , H04L27/22 , H04L27/233
CPC分类号： H04B1/707 , H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0065
摘要： A six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components comprises a code channel, a level channel and a phase channel each of which includes two accumulate and scale circuits. Each of the accumulate and scale circuits is connected to an I or a Q channel of the data which has been despread after being received from the communications receiver. The outputs of two of the accumulate and scale circuits are applied to a two to one multiplexor which is controlled by a command generator to provide a selectable output defining a clock error signal. The remaining four accumulate and scale circuits are connected to a first four to one multiplexor to provide a selectable output defining a clock error signal. The same four remaining outputs from said accumulate and scale circuits are connected to a second four to one multiplexor having an output defining a carrier error signal.
摘要翻译：一种被设计成与其他部件集成电路一起制造的六通道可编程数字解调器包括码通道，电平通道和相位通道，每个通道包括两个累积和标尺电路。每个累积和缩放电路连接到在从通信接收机接收到之后被解扩的数据的I或Q信道。两个累积和缩放电路的输出被施加到由指令发生器控制的两对多路复用器，以提供定义时钟误差信号的可选输出。剩余的四个累积和缩放电路连接到第一个四对多路复用器，以提供定义时钟误差信号的可选输出。来自所述累积和缩放电路的相同的四个剩余输出连接到具有定义载波误差信号的输出的第二四对一多路复用器。

9. 发明授权

US5022048A Programmable digital frequency-phase discriminator 失效
标题翻译：可编程数字频率鉴相器
公开(公告)号：US5022048A
公开(公告)日：1991-06-04
申请号：US559016
申请日：1990-07-26
申请人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
发明人： Samuel C. Kingston , Steven T. Barham , Harold L. Simonsen
IPC分类号： H04B1/66 , H04L27/00 , H04L27/14 , H04L27/22 , H04L27/233
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0057
摘要： A present invention novel frequency-phase discriminator has input channels for real and imaginary data which are coupled to two programmable despreaders. The first despreader has its real and imaginary outputs coupled to individual programmable data rate filters which have their individual outputs coupled to a quadrant detector that generates a phase angle direction signal and sign magnitude. The second despread has its real and imaginary outputs connected through individual programmable inverters to data rate filters which have their individual outputs coupled to a quadrant selector that selects error signal data rate information from one of four quadrant axes signals. A command generator is programmably coupled to the output of the quadrant detector and to the input of the quadrant selector and provides a selection signal to the quadrant selector which produces a frequency error signal output employed in a frequency lock loop or in a phase lock loop.
摘要翻译：本发明新颖的频率鉴相器具有耦合到两个可编程解扩器的实数和虚数据的输入通道。第一解扩器具有耦合到各个可编程数据速率滤波器的实部和虚拟输出，其各自的输出耦合到产生相位角方向信号和符号幅度的象限检测器。第二个解扩器具有通过单个可编程逆变器连接到数据速率滤波器的实际和虚拟输出，其数据速率滤波器的各自的输出耦合到从四象限轴信号之一选择误差信号数据速率信息的象限选择器。命令发生器可编程地耦合到象限检测器的输出端和象限选择器的输入端，并向象限选择器提供选择信号，该选择信号产生频率锁定环路或锁相环路中使用的频率误差信号输出。

10. 发明授权

US5452327A Programmable randomly tunable digital demodulator 失效
标题翻译：可编程随机可调数字解调器
公开(公告)号：US5452327A
公开(公告)日：1995-09-19
申请号：US179600
申请日：1993-12-28
申请人： Steven T. Barham , Mark C. Austin , Samuel C. Kingston
发明人： Steven T. Barham , Mark C. Austin , Samuel C. Kingston
IPC分类号： H04B1/69
CPC分类号： H04B1/69
摘要： A programmable randomly tunable digital demodulator is provided with a carrier recovery loop and a PN code clock recovery loop each having a programmable digital loop filter coupled in series therein. Each digital loop filter is controlled by a timing control which is capable of controlling the carrier frequency tuning and the PN tuning frequency under the control of a microprocessor. A replica PN generator is programmed to produce an epoch signal when the transmitted carrier frequency and/or chipping rate is varied in a pseudorandom manner and is coupled to the timing controls so that the modulator replicates the received variable rate signals.
摘要翻译：可编程随机可调谐数字解调器具有载波恢复环路和PN码时钟恢复环路，每个具有串行耦合的可编程数字环路滤波器。每个数字环路滤波器由能够在微处理器控制下控制载波频率调谐和PN调谐频率的定时控制来控制。当发送的载波频率和/或码片速率以伪随机方式变化并且耦合到定时控制时，复制PN发生器被编程为产生时标信号，使得调制器复制接收到的可变速率信号。

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