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1. 发明授权

US11996366B2 Semiconductor package including interposer 有权
公开(公告)号：US11996366B2
公开(公告)日：2024-05-28
申请号：US18144780
申请日：2023-05-08
申请人： Samsung Electronics Co., Ltd.
发明人： Seung-kwan Ryu , Yun-seok Choi
IPC分类号： H01L23/538 , H01L21/56 , H01L23/00
CPC分类号： H01L23/5384 , H01L21/568 , H01L23/5383 , H01L24/19
摘要： A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

2. 发明申请

US20170084561A1 SEMICONDUCTOR DEVICES WITH SOLDER-BASED CONNECTION TERMINALS AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20170084561A1
公开(公告)日：2017-03-23
申请号：US15262040
申请日：2016-09-12
申请人： Samsung Electronics Co., Ltd.
发明人： Sun-kyoung Seo , Seung-kwan Ryu , Ju-il Choi , Tae-je Cho , Yong-hwan Kwon
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/02205 , H01L2224/02215 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/10145 , H01L2224/11462 , H01L2224/1147 , H01L2224/11614 , H01L2224/1162 , H01L2224/11849 , H01L2224/13006 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13026 , H01L2224/13076 , H01L2224/13083 , H01L2224/13084 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13169 , H01L2224/13564 , H01L2224/16227 , H01L2224/16237 , H01L2224/73204 , H01L2224/81011 , H01L2224/81191 , H01L2224/81815 , H01L2924/05042 , H01L2924/05442 , H01L2924/07025 , H01L2924/00014 , H01L2924/014 , H01L2924/01082 , H01L2924/01083 , H01L2924/0103 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012
摘要： An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

3. 发明申请

US20220130767A1 SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20220130767A1
公开(公告)日：2022-04-28
申请号：US17573421
申请日：2022-01-11
申请人： Samsung Electronics Co., Ltd.
发明人： Seung-kwan Ryu , Yun-seok Choi
IPC分类号： H01L23/538 , H01L23/00 , H01L21/56
摘要： A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip

4. 发明授权

US11081440B2 Interposer and semiconductor package including the same 有权
公开(公告)号：US11081440B2
公开(公告)日：2021-08-03
申请号：US16563202
申请日：2019-09-06
申请人： Samsung Electronics Co., Ltd.
发明人： Yu-Kyung Park , Seung-kwan Ryu , Min-seung Yoon , Yun-seok Choi
IPC分类号： H01L23/498 , H01L25/18 , H01L21/48 , H01L23/538
摘要： An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

5. 发明授权

US10134702B2 Semiconductor chip, semiconductor package including the same, and method of manufacturing semiconductor chip 有权
公开(公告)号：US10134702B2
公开(公告)日：2018-11-20
申请号：US15494942
申请日：2017-04-24
申请人： Samsung Electronics Co., Ltd.
发明人： Sun-kyoung Seo , Seung-kwan Ryu , Cha-jea Jo , Tae-Je Cho
IPC分类号： H01L25/065 , H01L23/00 , H01L23/48
摘要： The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

6. 发明公开

US20240274588A1 SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20240274588A1
公开(公告)日：2024-08-15
申请号：US18641581
申请日：2024-04-22
申请人： Samsung Electronics Co., Ltd.
发明人： Seung-kwan Ryu , Yun-seok Choi
IPC分类号： H01L25/18 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498
CPC分类号： H01L25/18 , H01L23/3128 , H01L23/481 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L21/565 , H01L21/568 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2924/1815
摘要： A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

7. 发明授权

US11705391B2 Interposer and semiconductor package including the same 有权
公开(公告)号：US11705391B2
公开(公告)日：2023-07-18
申请号：US17316028
申请日：2021-05-10
申请人： Samsung Electronics Co., Ltd.
发明人： Yu-Kyung Park , Seung-kwan Ryu , Min-seung Yoon , Yun-seok Choi
IPC分类号： H01L23/498 , H01L25/18 , H01L21/48 , H01L23/538
CPC分类号： H01L23/49838 , H01L21/481 , H01L21/486 , H01L21/4853 , H01L23/49827 , H01L23/49894 , H01L23/5384 , H01L25/18
摘要： An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

8. 发明申请

US20200168550A1 SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20200168550A1
公开(公告)日：2020-05-28
申请号：US16556538
申请日：2019-08-30
申请人： Samsung Electronics Co., Ltd.
发明人： Seung-kwan Ryu , Yun-seok Choi
IPC分类号： H01L23/538 , H01L21/56 , H01L23/00
摘要： A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip

9. 发明公开

US20230275029A1 SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20230275029A1
公开(公告)日：2023-08-31
申请号：US18144780
申请日：2023-05-08
申请人： Samsung Electronics Co., Ltd.
发明人： Seung-kwan Ryu , Yun-seok Choi
IPC分类号： H01L23/538 , H01L23/00 , H01L21/56
CPC分类号： H01L23/5384 , H01L21/568 , H01L23/5383 , H01L24/19
摘要： A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

10. 发明授权

US11676902B2 Semiconductor package including interposer 有权
公开(公告)号：US11676902B2
公开(公告)日：2023-06-13
申请号：US17573421
申请日：2022-01-11
申请人： Samsung Electronics Co., Ltd.
发明人： Seung-kwan Ryu , Yun-seok Choi
IPC分类号： H01L23/538 , H01L21/56 , H01L23/00
CPC分类号： H01L23/5384 , H01L21/568 , H01L23/5383 , H01L24/19
摘要： A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

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