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1. 发明授权

US11610966B2 Semiconductor devices 有权
公开(公告)号：US11610966B2
公开(公告)日：2023-03-21
申请号：US16694031
申请日：2019-11-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jung-Han Lee , Jae-Hwan Lee , Sang-Su Kim , Hwan-Wook Choi , Tae-Jong Lee , Seung-Mo Ha
IPC分类号： H01L29/06 , H01L27/088 , H01L21/8234
摘要： A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

2. 发明申请

US20170018645A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20170018645A1
公开(公告)日：2017-01-19
申请号：US15224313
申请日：2016-07-29
申请人： Samsung Electronics Co., Ltd.
发明人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
IPC分类号： H01L29/78 , H01L29/66 , H01L21/02 , H01L29/165 , H01L29/08 , H01L29/16 , H01L29/161 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/823431 , H01L21/823437 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
摘要翻译：形成半导体器件的方法可以包括形成在衬底上沿第一方向延伸的鳍式有源图案，鳍型有源图案包括在衬底上的下图案和下图案上的上图案。场绝缘层形成在衬底上，翅片型有源图案的侧壁和远离衬底的部分上部图案远离场绝缘层的顶表面。形成与翅片型有源图案相交并且沿与第一方向不同的第二方向延伸的伪栅极图案。所述方法包括在伪栅极图案的侧壁上形成虚拟栅极间隔物，在虚拟栅极图案的两侧上形成鳍状有源图案中的凹槽，并在虚拟栅极图案的两侧形成源区和漏极区。

3. 发明授权

US09324812B2 Semiconductor device including nanowire transistor 有权
标题翻译：半导体器件包括纳米线晶体管
公开(公告)号：US09324812B2
公开(公告)日：2016-04-26
申请号：US14489418
申请日：2014-09-17
申请人： Samsung Electronics Co., Ltd.
发明人： Jung-Gil Yang , Sang-Su Kim , Sung-Gi Hur
IPC分类号： H01L29/06 , H01L29/267 , H01L29/20 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/786 , H01L21/8234 , H01L27/088 , H01L27/092
CPC分类号： H01L29/0673 , H01L21/02233 , H01L21/823412 , H01L27/088 , H01L27/092 , H01L29/0642 , H01L29/0676 , H01L29/068 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/267 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/66795 , H01L29/785 , H01L29/78684 , H01L29/78696
摘要： A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.
摘要翻译：半导体器件包括至少一个纳米线，其被布置在衬底上，延伸成与衬底间隔开，并且包括通道区域，围绕沟道区域的至少一部分的栅极和栅极电介质膜，栅极电介质膜是设置在通道区域和栅极之间。接触至少一个纳米线的一端的源/漏区形成在从衬底延伸到至少一个纳米线的一端的半导体层中。在衬底和至少一个纳米线之间形成绝缘间隔物。绝缘垫片设置在栅极和源极/漏极区域之间，并且由与栅极电介质膜的材料不同的材料形成。

4. 发明授权

US11515390B2 Semiconductor devices 有权
公开(公告)号：US11515390B2
公开(公告)日：2022-11-29
申请号：US16993514
申请日：2020-08-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jung-Han Lee , Jae-Hwan Lee , Sang-Su Kim , Hwan-Wook Choi , Tae-Jong Lee , Seung-Mo Ha
IPC分类号： H01L29/06 , H01L27/088 , H01L21/8234
摘要： A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

5. 发明授权

US10411129B2 Methods of fabricating semiconductor devices 有权
公开(公告)号：US10411129B2
公开(公告)日：2019-09-10
申请号：US15877563
申请日：2018-01-23
申请人： Samsung Electronics Co., Ltd.
发明人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
IPC分类号： H01L31/072 , H01L31/109 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/165 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/16 , H01L29/161
摘要： Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

6. 发明授权

US09978835B2 Semiconductor device including nanowire transistor 有权
公开(公告)号：US09978835B2
公开(公告)日：2018-05-22
申请号：US15339690
申请日：2016-10-31
申请人： Samsung Electronics Co., Ltd.
发明人： Jung-Gil Yang , Sang-Su Kim , Sung-Gi Hur
IPC分类号： H01L29/06 , H01L29/267 , H01L29/786 , H01L29/423 , H01L29/20 , H01L21/02 , H01L29/66 , H01L27/088 , H01L29/78 , H01L29/08 , H01L29/16 , H01L29/161 , H01L21/8234 , H01L27/092
CPC分类号： H01L29/0673 , H01L21/02233 , H01L21/823412 , H01L27/088 , H01L27/092 , H01L29/0642 , H01L29/0676 , H01L29/068 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/267 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/66795 , H01L29/785 , H01L29/78684 , H01L29/78696
摘要： A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

7. 发明申请

US20190019864A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20190019864A1
公开(公告)日：2019-01-17
申请号：US16124521
申请日：2018-09-07
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jung-Han Lee , Jae-Hwan Lee , Sang-Su Kim , Hwan-Wook Choi , Tae-Jong Lee , Seung-Mo Ha
IPC分类号： H01L29/06 , H01L21/8234 , H01L27/088
摘要： A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

8. 发明授权

US09893186B2 Methods of fabricating semiconductor devices 有权
公开(公告)号：US09893186B2
公开(公告)日：2018-02-13
申请号：US15224313
申请日：2016-07-29
申请人： Samsung Electronics Co., Ltd.
发明人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
IPC分类号： H01L31/072 , H01L31/109 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/165 , H01L21/02 , H01L21/8238 , H01L29/08 , H01L29/16 , H01L29/161 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/823431 , H01L21/823437 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

9. 发明授权

US09219064B2 Semiconductor devices having a nanowire channel structure 有权
标题翻译：具有纳米线通道结构的半导体器件
公开(公告)号：US09219064B2
公开(公告)日：2015-12-22
申请号：US14163148
申请日：2014-01-24
申请人： Samsung Electronics Co., Ltd.
发明人： Sang-Su Kim
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823412 , H01L21/823807 , H01L27/092 , H01L29/0673 , H01L29/42392
摘要： A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.
摘要翻译：半导体器件包括第一晶体管和第二晶体管。第一晶体管包括延伸穿过第一栅电极并在第一源极和漏极区之间的第一纳米线。第二晶体管包括延伸穿过第二栅极电极和第二源极和漏极区域之间的第二纳米线。第一纳米线在第一方向上具有第一尺寸，在第二方向上具有第二尺寸，并且第二纳米线在第一方向上具有第二尺寸，并且在第二方向上具有基本上第二尺寸。第一个纳米线有一个第一个电流，第二个纳米线有一个电流。基于第一和第二纳米线的尺寸之差，第一纳米线的导通电流可以基本上等于第二纳米线的导通电流。在另一种布置中，导通电流可以不同。

10. 发明授权

US09984925B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US09984925B2
公开(公告)日：2018-05-29
申请号：US15182024
申请日：2016-06-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yong-Ho Jeon , Sang-Su Kim , Cheol Kim , Yong-Suk Tak , Myung-Geun Song , Gi-Gwan Park
IPC分类号： H01L21/768 , H01L21/8238 , H01L23/535 , H01L27/092 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823431 , H01L21/823468 , H01L21/823475 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823864 , H01L21/823871 , H01L23/535 , H01L27/0886 , H01L27/0924 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/4966 , H01L29/66545 , H01L29/7848
摘要： A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

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