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1. 发明申请

US20220310151A1 MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME 有权
公开(公告)号：US20220310151A1
公开(公告)日：2022-09-29
申请号：US17807163
申请日：2022-06-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dae-Sik MOON , Gil-Hoon CHA , Ki-Seonk OH , Chang-Kyo LEE , Yeon-Kyu CHOI , Jung-Hwan CHOI , Kyung-Soo HA , Seok-Hun HYUN
IPC分类号： G11C11/4076 , G11C11/409 , G06F3/06 , G11C7/22
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

2. 发明申请

US20210327476A1 MEMORY DEVICE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY DEVICE 有权
公开(公告)号：US20210327476A1
公开(公告)日：2021-10-21
申请号：US17355765
申请日：2021-06-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： DONGHUN LEE , Daesik MOON , Young-Soo SOHN , Young-Hoon SON , Ki-Seok OH , Changkyo LEE , Hyun-Yoon CHO , Kyung-Soo HA , Seokhun HYUN
IPC分类号： G11C7/10 , G06F3/06
摘要： A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

3. 发明申请

US20140219036A1 EQUALIZER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：均衡器和半导体存储器件包括它们
公开(公告)号：US20140219036A1
公开(公告)日：2014-08-07
申请号：US14165990
申请日：2014-01-28
申请人： Samsung Electronics Co., Ltd.
发明人： Dae-Hyun KIM , Seung-Jun BAE , Kyung-Soo HA
IPC分类号： G11C7/12 , H03K19/094 , G11C7/22
CPC分类号： G11C7/22 , G11C7/1048 , G11C7/1057 , H03K19/00361 , H03K19/09429
摘要： Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.
摘要翻译：提供了一种均衡器和包括该均衡器的半导体存储器件。均衡器包括延迟电路和反相电路。延迟电路被配置为响应于选择信号输出延迟施加到输入/输出节点的输入信号的延迟信号和反相输入信号的反相信号之一。反相电路被配置为反转从延迟电路提供的信号并将反相信号输出到输入/输出节点。均衡器被配置为使得当延迟电路输出延迟信号时，均衡器用作放大输入信号并输出放大的输入信号的感应偏置电路，并且当延迟电路输出反相信号时，均衡器作为锁存器电路存储和输出输入信号。

4. 发明申请

US20230012525A1 METHOD OF OPERATING MEMORY DEVICE, METHOD OF OPERATING MEMORY CONTROLLER AND MEMORY SYSTEM 有权
公开(公告)号：US20230012525A1
公开(公告)日：2023-01-19
申请号：US17692953
申请日：2022-03-11
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ki-Heung KIM , Jun Hyung KIM , Chang-Yong LEE , Sang Uhn CHA , Kyung-Soo HA
IPC分类号： G06F11/10 , G06F11/07 , G06F3/06
摘要： A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

5. 发明申请

US20190181109A1 SEMICONDUCTOR MEMORY INCLUDING PADS ARRANGED IN PARALLEL 审中-公开
公开(公告)号：US20190181109A1
公开(公告)日：2019-06-13
申请号：US16036198
申请日：2018-07-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sihong KIM , Young-Hoon SON , Taeyoung OH , Kyung-Soo HA
IPC分类号： H01L23/00 , G11C5/06 , G11C8/10
摘要： A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.

6. 发明申请

US20160134285A1 ON-DIE TERMINATION CIRCUIT AND ON-DIE TERMINATION METHOD 有权
标题翻译：端接终止电路和端接终止方法
公开(公告)号：US20160134285A1
公开(公告)日：2016-05-12
申请号：US14742219
申请日：2015-06-17
申请人： Samsung Electronics Co., Ltd.
发明人： Kyung-Soo HA
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H03K19/0005 , H03K19/00369
摘要： An ODT circuit capable of generating an OCD/ODT code and/or a reference voltage adaptively adjusted according to a system environment is disclosed. The ODT circuit comprises a system environment detector, an OCD/ODT replica circuit, an OCD/ODT code generator and an OCD/ODT unit. The system environment detector detects a supply voltage to generate a voltage code, detects an operating temperature to generate a temperature code, and detects an operating frequency to generate a frequency code. The OCD/ODT code generator generates a pull-up code and a pull-down code currently optimized for a semiconductor memory device based on a pull-up reference voltage, a pull-down reference voltage, the voltage code, the temperature code and the frequency code.
摘要翻译：公开了能够产生根据系统环境自适应调整的OCD / ODT码和/或参考电压的ODT电路。 ODT电路包括系统环境检测器，OCD / ODT复制电路，OCD / ODT码发生器和OCD / ODT单元。系统环境检测器检测电源电压以产生电压代码，检测工作温度以产生温度代码，并检测工作频率以产生频率代码。 OCD / ODT代码生成器根据上拉参考电压，下拉参考电压，电压代码，温度代码和对于半导体存储器件的下拉代码生成当前针对半导体存储器件优化的上拉代码和下拉代码频码

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