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1. 发明申请

US20040197991A1 Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating the same 失效
标题翻译：金属 - 绝缘体 - 金属电容器的双镶嵌互连及其制造方法
公开(公告)号：US20040197991A1
公开(公告)日：2004-10-07
申请号：US10799292
申请日：2004-03-12
申请人： Samsung Electronics Co., Ltd.
发明人： Kyoung-woo Lee , Soo-geun Lee
IPC分类号： H01L021/8242
CPC分类号： H01L21/76807 , H01L23/5223 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.
摘要翻译：提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。在该结构中，在通孔级IMD上形成MIM电容器。在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

2. 发明申请

US20040135261A1 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US20040135261A1
公开(公告)日：2004-07-15
申请号：US10744277
申请日：2003-12-23
申请人： Samsung Electronics Co., Ltd.
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L023/48
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

3. 发明申请

US20040132291A1 Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler 有权
标题翻译：使用混合低k电介质和无碳无机填料制造微电子器件的双镶嵌互连的方法
公开(公告)号：US20040132291A1
公开(公告)日：2004-07-08
申请号：US10625007
申请日：2003-07-23
申请人： Samsung Electronics Co., Ltd.
发明人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H01L21/76808
摘要： A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.
摘要翻译：提供了一种制造双镶嵌互连的方法。在具有3.3或更小的介电常数的混合电介质层中形成双镶嵌区域，并且使用无碳无机材料作为通孔填料。本发明改进了双镶嵌互连的电性能并使缺陷最小化。

4. 发明申请

US20030109132A1 Method for forming dual damascene structure in semiconductor device 失效
标题翻译：在半导体器件中形成双镶嵌结构的方法
公开(公告)号：US20030109132A1
公开(公告)日：2003-06-12
申请号：US10233812
申请日：2002-09-03
申请人： Samsung Electronics Co., Ltd.
发明人： Kyoung-woo Lee
IPC分类号： H01L021/44 , H01L021/4763
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813
摘要： A method for forming a dual damascene structure in a semiconductor device, which is capable of preventing defects in node segregation between damascene interconnections and reducing parasitic capacitance, is provided. The method includes sequentially depositing an insulating structure layer including a via level insulating layer and a trench level insulating layer and a hard mask layer on a semiconductor substrate on which an underlying layer including a contact plug is formed, forming a via hole on the via level insulating layer using the hard mask layer, and forming a trench connected to the via hole in the insulating structure layer using the hard mask layer. A predetermined upper portion of the insulating structure layer and the hard mask layer are removed when the trench and the via hole are formed.
摘要翻译：提供了一种在半导体器件中形成双镶嵌结构的方法，其能够防止镶嵌互连之间的节点偏离和减小寄生电容的缺陷。该方法包括在其上形成有包括接触插塞的下层的半导体衬底上依次沉积包括通孔层绝缘层和沟槽级绝缘层和硬掩模层的绝缘结构层，在通孔级上形成通孔使用硬掩模层的绝缘层，并且使用硬掩模层形成与绝缘结构层中的通孔连接的沟槽。当形成沟槽和通孔时，去除绝缘结构层和硬掩模层的预定上部。

5. 发明申请

US20020173143A1 Method for forming metal wiring layer of semiconductor device 有权
标题翻译：用于形成半导体器件的金属布线层的方法
公开(公告)号：US20020173143A1
公开(公告)日：2002-11-21
申请号：US10114274
申请日：2002-04-02
申请人： Samsung Electronics Co., Ltd.
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
IPC分类号： H01L021/4763
CPC分类号： H01L21/76808 , H01L21/76813 , H01L21/76835
摘要： A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate. The organic material layer and the hard mask layer on the interlayer insulating layer are etched using the second photoresist pattern as an etching mask. The second photoresist pattern and the organic material layer are simultaneously removed. A wiring region having the second width and a via hole having the first width are formed by etching the interlayer insulating layer using the hard mask layer as an etching mask.
摘要翻译：提供了一种使用双镶嵌工艺在半导体器件中形成金属布线层的方法。在具有导电层的半导体衬底上依次形成阻挡层，层间绝缘层和硬掩模层。包括具有第一宽度的第一开口的第一光致抗蚀剂图案形成在硬掩模层上。使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻硬掩模层和层间绝缘层的部分，从而形成具有第一宽度的部分通孔。去除第一光致抗蚀剂图案。在半导体基板上涂布有机材料层，其中形成有部分通孔以用有机材料层填充部分通孔。在涂覆的半导体衬底上形成第二光致抗蚀剂图案，该第二光致抗蚀剂图案包括与部分通路孔对准的第二开口，并具有大于第一宽度的第二宽度。使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻层间绝缘层上的有机材料层和硬掩模层。同时去除第二光致抗蚀剂图案和有机材料层。通过使用硬掩模层作为蚀刻掩模蚀刻层间绝缘层，形成具有第二宽度的布线区域和具有第一宽度的通孔。

6. 发明申请

US20020168849A1 Method of manufacturing interconnection line in semiconductor device 有权
标题翻译：在半导体器件中制造互连线的方法
公开(公告)号：US20020168849A1
公开(公告)日：2002-11-14
申请号：US10081661
申请日：2002-02-22
申请人： Samsung Electronics Co., Ltd.
发明人： Soo-geun Lee , Hong-jae Shin , Kyoung-woo Lee , Jae-hak Kim
IPC分类号： H01L021/44 , H01L021/4763
CPC分类号： H01L21/76808 , H01L21/31111 , H01L21/31116 , H01L21/31144
摘要： A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.
摘要翻译：提供了一种在半导体器件中形成互连线的方法。在形成在半导体衬底上的下导电层上形成第一蚀刻阻挡层。在第一蚀刻停止件上形成第一层间绝缘层。在第一层间绝缘层上形成第二蚀刻阻挡层。在第二蚀刻停止件上形成第二层间绝缘层。使用第一蚀刻停止器作为蚀刻停止点，依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下导电层对准的通孔。形成保护层以保护暴露在通孔底部的第一蚀刻终止部分。使用第二蚀刻停止器蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点，以形成连接到通孔的沟槽。保护层被去除。位于通孔底部的第一蚀刻停止部分被去除。形成填充通孔和沟槽并与下导电层电连接的上导电层。

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