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1. 发明申请

US20020106891A1 Method of fabricating semiconductor devices having low dielectric interlayer insulation layer 失效
标题翻译：制造具有低介电层间绝缘层的半导体器件的方法
公开(公告)号：US20020106891A1
公开(公告)日：2002-08-08
申请号：US09994508
申请日：2001-11-27
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Hak Kim , Hong-Jae Shin , Soo-Geun Lee , Kyoung-Woo Lee
IPC分类号： H01L021/4763 , H01L023/48 , H01L023/52 , H01L021/469
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02137 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/0234 , H01L21/02362 , H01L21/3144 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.
摘要翻译：公开了一种制造具有低介电常数的半导体器件的方法。根据该方法，形成碳氧化硅层，用等离子体处理并图案化。碳硅氧化物层通过涂布法或CVD法如PECVD法形成。通过供给选自He，H 2，N 2 O，NH 3，N 2，O 2和Ar的至少一种气体来进行用等离子体处理碳氧化硅层。希望在形成硅碳化硅层之后，通过原位法将等离子体施加在PECVD器件中的碳氧化硅层。在封盖层进一步堆叠和图案化的情况下，期望用H 2等离子体处理。即使在由硅碳化硅层和双镶嵌工艺的有机聚合物基团的涂层形成层间绝缘的情况下，期望在形成涂层之前进行等离子体处理。

2. 发明申请

US20030176056A1 Method for forming metal wiring layer of semiconductor device 有权
标题翻译：用于形成半导体器件的金属布线层的方法
公开(公告)号：US20030176056A1
公开(公告)日：2003-09-18
申请号：US10392710
申请日：2003-03-20
申请人： Samsung Electronics Co., Ltd.
发明人： Kyoung-Woo Lee , Hong-Jae Shin , Jae-Hak Kim , Soo-Geun Lee
IPC分类号： H01L021/4763
CPC分类号： H01L21/76808 , H01L21/76813
摘要： Methods for forming a metal wiring layer in a semiconductor device using a dual damascene process. In one aspect, a method for forming metal wiring in a semiconductor device comprises: forming a stopper layer on a semiconductor substrate that has a conductive layer formed thereon; forming an interlayer dielectric layer on the stopper layer; forming a hard mask layer on the interlayer dielectric layer; forming a first photoresist pattern on the hard mask layer, the first photoresist pattern having a first opening corresponding to the conductive layer; etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask to form a via hole in the interlayer dielectric layer through which a portion of the stopper layer is exposed; removing the first photoresist pattern; filling the via hole with an intermediary material layer; etching a portion of the hard mask layer to form a hard mask pattern that defines a wiring region, wherein the hard mask pattern comprises a second opening that overlaps the entire via hole or at least a portion of the via hole; removing the intermediary material layer from the via hole; forming the wiring region by etching a portion of the interlayer dielectric layer using the hard mask pattern as an etching mask; removing a portion of the stopper layer exposed by the via hole; and filling the via hole and the wiring region with a conductive material.
摘要翻译：使用双镶嵌工艺在半导体器件中形成金属布线层的方法。一方面，在半导体器件中形成金属布线的方法包括：在其上形成有导电层的半导体衬底上形成阻挡层; 在所述阻挡层上形成层间绝缘层; 在所述层间介质层上形成硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂图案，所述第一光致抗蚀剂图案具有对应于所述导电层的第一开口; 使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，以在阻挡层的一部分暴露的层间绝缘层中形成通孔; 去除第一光致抗蚀剂图案; 用中间材料层填充通孔; 蚀刻硬掩模层的一部分以形成限定布线区域的硬掩模图案，其中硬掩模图案包括与整个通孔或通孔的至少一部分重叠的第二开口; 从所述通孔中去除所述中间材料层; 通过使用硬掩模图案作为蚀刻掩模蚀刻层间电介质层的一部分来形成布线区域; 去除由通孔露出的阻挡层的一部分; 以及用导电材料填充所述通孔和所述布线区域。

3. 发明申请

US20020033486A1 Method for forming an interconnection line using a hydrosilsesquioxane (HSQ) layer as an interlayer insulating layer 审中-公开
标题翻译：使用氢化倍半硅氧烷（HSQ）层作为层间绝缘层形成互连线的方法
公开(公告)号：US20020033486A1
公开(公告)日：2002-03-21
申请号：US09919628
申请日：2001-07-30
申请人： Samsung Electronics Co., Ltd.
发明人： Won-Jin Kim , Soo-Geun Lee , Hong-Jae Shin , Jae-Hyun Han , Jae-Hak Kim , Ho-Kyu Kang
IPC分类号： H01L029/74 , H01L031/111
CPC分类号： H01L21/76829 , H01L21/02134 , H01L21/02282 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/31058 , H01L21/3124 , H01L21/76801 , H01L21/7681 , H01L21/76826 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for forming interconnection lines using a hydrosilsesquioxane (HSQ) layer as an interlayer insulating layer. A HSQ layer is formed over a semiconductor substrate and an entire surface of the HSQ layer is subjected to plasma treatment. It is then possible to pattern the HSQ layer using photo etching, for the bond structure density of an upper part of the HSQ layer has been increased due to the plasma treatment. An opening is formed by patterning the treated HSQ layer and then a conductive layer filling the opening is formed. In this manner, a multilayer interconnection structure can be formed with a low dielectric layer made of HSQ, thereby reducing the resistance-capacitance (RC) delay.
摘要翻译：公开了使用氢化硅倍半氧烷（HSQ）层作为层间绝缘层形成互连线的方法。在半导体衬底上形成HSQ层，并对HSQ层的整个表面进行等离子体处理。然后可以利用光蚀刻对HSQ层进行图案化，由于等离子体处理，HSQ层的上部的键结构密度已经增加。通过对经处理的HSQ层进行图案化形成开口，然后形成填充开口的导电层。以这种方式，可以用由HSQ制成的低电介质层形成多层互连结构，从而降低电阻 - 电容（RC）延迟。

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