会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Liquid crystal display having contact holes adjacently disposed in thin film transistor forming region
    • 具有相邻设置在薄膜晶体管形成区域中的接触孔的液晶显示器
    • US09568790B2
    • 2017-02-14
    • US14476570
    • 2014-09-03
    • Samsung Display Co., Ltd.
    • Yun HeoBong-Jun LeeDong Wuuk SeoJong Woong Chang
    • G02F1/136G02F1/1362G02F1/1337
    • G02F1/136227G02F1/133707G02F2201/40
    • A liquid crystal display includes: a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates. The pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region.
    • 液晶显示器包括:第一基板; 位于第一基板上的栅极线和公共电压线; 栅极线和公共电压线上的栅极绝缘层; 栅极绝缘层上的半导体层; 数据线和漏电极,位于半导体层上; 数据线和漏电极上的像素电极; 像素电极上的钝化层; 钝化层上的公共电极; 第二基板; 以及插入在第一和第二基板之间的液晶层。 像素电极经由第一接触孔接触漏极,公共电极经由栅极绝缘层和钝化层中的第二接触孔接触公共电压线,并且第一和第二接触孔相邻地设置在薄膜 晶体管形成区域。
    • 10. 发明授权
    • Display panel
    • 显示面板
    • US09589519B2
    • 2017-03-07
    • US14203272
    • 2014-03-10
    • Samsung Display Co., Ltd.
    • Jung Hwan HwangBeom Jun KimSeong Yeol SynBong-Jun LeeYou Mee Hyun
    • G09G3/36G11C19/28
    • G09G3/2092G09G3/3648G09G3/3677G09G2300/0809G09G2310/0286G11C19/28
    • A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
    • 提供显示面板。 显示面板包括包括栅线和数据线的显示区域,以及连接到栅极线的端子的栅极驱动器。 栅极驱动器包括集成在衬底上的多个级,并且每个级包括逆变器单元,输出单元和Q结点稳定单元。 输出单元包括第一晶体管和第一电容器,其中第一晶体管包括用于接收时钟信号的输入端子,连接到节点Q的控制端子和连接到栅极电压输出端子的输出端子以输出栅极 电压。 当输出单元输出栅极导通电压时,Q节点稳定单元中的晶体管的Vgs电压具有等于或小于0V的值。