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1. 发明授权

US07761068B2 System and method for a time alignment analog notch 有权
标题翻译：时间对齐模拟量程的系统和方法
公开(公告)号：US07761068B2
公开(公告)日：2010-07-20
申请号：US11728227
申请日：2007-03-23
申请人： Sameh Sameer Rezeq , Khurram Waheed , Sudheer Vemulapalli
发明人： Sameh Sameer Rezeq , Khurram Waheed , Sudheer Vemulapalli
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H03F3/217 , H03F3/193 , H03K5/133
摘要： System and method for creating a time alignment analog notch. An embodiment includes a digital power amplifier coupled to an enable signal line and to a digital control bits bus, and a matching network coupled to the digital power amplifier. The matching network to provide impedance matching and the digital power amplifier to produce a current based on a value on the digital control bits bus. The digital power amplifier comprises a selection circuit and a plurality of transistors. The transistors, controlled by outputs of the selection circuit, provide a current based on the value on the digital control bits bus. The adjustment of a delay between a signal on the enable signal line and the values on the digital control bits bus creates an analog notch at about Fs/2, where Fs is a sampling frequency of a sigma-delta modulator used to modulate data provided to the digital power amplifier.
摘要翻译：用于创建时间对齐模拟切口的系统和方法。实施例包括耦合到使能信号线和数字控制位总线的数字功率放大器以及耦合到数字功率放大器的匹配网络。匹配网络提供阻抗匹配和数字功率放大器根据数字控制位总线上的值产生电流。数字功率放大器包括选择电路和多个晶体管。由选择电路的输出控制的晶体管基于数字控制位总线上的值提供电流。在使能信号线上的信号与数字控制位总线上的值之间的延迟的调整在大约Fs / 2处产生模拟陷波，其中Fs是用于调制提供给数字功率放大器。

2. 发明申请

US20080233898A1 System and method for a time alignment analog notch 有权
标题翻译：时间对齐模拟量程的系统和方法
公开(公告)号：US20080233898A1
公开(公告)日：2008-09-25
申请号：US11728227
申请日：2007-03-23
申请人： Sameh Sameer Rezeq , Khurram Waheed , Sudheer Vemulapalli
发明人： Sameh Sameer Rezeq , Khurram Waheed , Sudheer Vemulapalli
IPC分类号： H03C1/52 , H03F3/217 , H03K3/017
CPC分类号： H03F3/217 , H03F3/193 , H03K5/133
摘要： System and method for creating a time alignment analog notch. An embodiment includes a digital power amplifier coupled to an enable signal line and to a digital control bits bus, and a matching network coupled to the digital power amplifier. The matching network to provide impedance matching and the digital power amplifier to produce a current based on a value on the digital control bits bus. The digital power amplifier comprises a selection circuit and a plurality of transistors. The transistors, controlled by outputs of the selection circuit, provide a current based on the value on the digital control bits bus. The adjustment of a delay between a signal on the enable signal line and the values on the digital control bits bus creates an analog notch at about Fs/2, where Fs is a sampling frequency of a sigma-delta modulator used to modulate data provided to the digital power amplifier.
摘要翻译：用于创建时间对齐模拟切口的系统和方法。实施例包括耦合到使能信号线和数字控制位总线的数字功率放大器以及耦合到数字功率放大器的匹配网络。匹配网络提供阻抗匹配和数字功率放大器根据数字控制位总线上的值产生电流。数字功率放大器包括选择电路和多个晶体管。由选择电路的输出控制的晶体管基于数字控制位总线上的值提供电流。在使能信号线上的信号与数字控制位总线上的值之间的延迟的调整在大约Fs / 2处产生模拟陷波，其中Fs是用于调制提供给数字功率放大器。

3. 发明申请

US20080315960A1 Digital Phase Locked Loop with Gear Shifting 有权
标题翻译：数字锁相环与齿轮换档
公开(公告)号：US20080315960A1
公开(公告)日：2008-12-25
申请号：US12137332
申请日：2008-06-11
申请人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
发明人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
IPC分类号： H03L7/099 , H03B5/12
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha-α) and an integral loop gain control having a programmable loop gain coefficient (rho-ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。连接可编程滤波器以接收相位误差样本并连接以提供具有对可控振荡器的增益和相位裕度的滤波输出。可编程滤波器包括具有可编程环路增益系数（α-α）的比例环路增益控制和具有可编程环路增益系数（rho-rho））的积分环路增益控制。 Alpha和rho被配置为同时编程地改变，并且被选择为使得增益改变并且相位裕度保持基本上不变

4. 发明授权

US07777576B2 Digital phase locked loop with gear shifting 有权
标题翻译：带变速的数字锁相环
公开(公告)号：US07777576B2
公开(公告)日：2010-08-17
申请号：US12137332
申请日：2008-06-11
申请人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
发明人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
IPC分类号： H03L7/093 , H03L7/16
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha—α) and an integral loop gain control having a programmable loop gain coefficient (rho—ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。连接可编程滤波器以接收相位误差样本并连接以提供具有对可控振荡器的增益和相位裕度的滤波输出。可编程滤波器包括具有可编程环路增益系数（α-α）的比例环路增益控制和具有可编程环路增益系数（rho- rgr）的积分环路增益控制。 Alpha和rho被配置为同时编程地改变，并且被选择为使得增益改变并且相位裕度保持基本上不变。

5. 发明申请

US20060103566A1 Circuit for high-resolution phase detection in a digital RF processor 有权
标题翻译：用于数字RF处理器中高分辨率相位检测的电路
公开(公告)号：US20060103566A1
公开(公告)日：2006-05-18
申请号：US11274965
申请日：2005-11-15
申请人： Sudheer Vemulapalli , John Wallberg , Prasant Vallur , Robert Staszewski
发明人： Sudheer Vemulapalli , John Wallberg , Prasant Vallur , Robert Staszewski
IPC分类号： H03M1/12
CPC分类号： H04L27/361 , G04F10/005 , H03L7/091
摘要： A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.
摘要翻译：一种新颖的时间数字转换器（TDC），用作数字无线电处理器内的全数字PLL中的相位/频率检测器和电荷泵替换。 TDC内核基于伪差分数字架构，使其对NMOS和PMOS晶体管不匹配不敏感。时间转换分辨率等于CMOS的逆变器传播延迟，例如20 ps，这是CMOS中最优的逻辑电平再生定时。 TDC自校准，估计精度优于1％。 TDC电路还可以用作大型SoC模具中模拟电路的CMOS工艺强度估计器。该电路还采用电源管理电路，将功耗降至非常低的水平。

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