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1. 发明申请

US20130093505A1 ON-CHIP VOLTAGE REGULATOR 有权
标题翻译：片内电压调节器
公开(公告)号：US20130093505A1
公开(公告)日：2013-04-18
申请号：US13275310
申请日：2011-10-17
申请人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
发明人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.
摘要翻译：用于调节SoC的电压的数字逻辑控制器包括用于接收具有在SoC的工作条件范围内恒定的第一特性的参考信号的第一输入端和用于接收第二信号的第二输入端表示SoC的运行状况的属性。第二个属性可能在SoC的一系列操作条件下变化。比较器比较第一和第二特性和数字逻辑控制器，基于该比较，输出到调节信号到电压调节器，以调节在目标电压或其附近的目标电压的电压，该目标电压高于最低工作电压 SoC。

2. 发明授权

US08487805B1 Successive approximation analog-to-digital converter 有权
标题翻译：逐次近似模数转换器
公开(公告)号：US08487805B1
公开(公告)日：2013-07-16
申请号：US13403945
申请日：2012-02-23
申请人： Sunny Gupta , Kumar Abhishek , Kushal Kamal , Samaksh Sinha
发明人： Sunny Gupta , Kumar Abhishek , Kushal Kamal , Samaksh Sinha
IPC分类号： H03M1/34
CPC分类号： H03M1/007 , H03M1/46
摘要： An analog-to-digital converter (ADC) converts an analog input signal to a digital output signal by sampling an analog input signal to obtain an analog sample and then converting the analog sample to the digital output signal using a successive approximation algorithm. The method decreases ADC conversion time and increases ADC throughput.
摘要翻译：模数转换器（ADC）通过采样模拟输入信号将模拟输入信号转换为数字输出信号，以获得模拟采样，然后使用逐次逼近算法将模拟采样转换为数字输出信号。该方法可减少ADC转换时间并提高ADC吞吐量。

3. 发明授权

US08760202B1 System for generating clock signal 有权
标题翻译：用于产生时钟信号的系统
公开(公告)号：US08760202B1
公开(公告)日：2014-06-24
申请号：US13895344
申请日：2013-05-15
申请人： Samaksh Sinha , Niti Gupta , Sunny Gupta
发明人： Samaksh Sinha , Niti Gupta , Sunny Gupta
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L2207/08
摘要： A system for generating a clock signal includes a phase-locked loop (PLL) and a voltage storage circuit. The PLL includes a voltage-controlled oscillator (VCO) that generates a clock signal based on a control voltage. The voltage storage circuit includes a unity-gain amplifier (UGA) and first, second and third switches. The first switch connects an input terminal of the UGA and an input of the VCO to sample the control voltage before the PLL transitions from RUN mode to STOP mode. The second switch connects the input and output terminals of the UGA to store the sampled control voltage when the PLL is in STOP mode. The third switch connects the output terminal of the UGA to the input terminal of a low pass filter (LPF) to provide the stored control voltage to the LPF when the PLL transitions from the STOP mode to the RUN mode.
摘要翻译：用于产生时钟信号的系统包括锁相环（PLL）和电压存储电路。 PLL包括基于控制电压产生时钟信号的压控振荡器（VCO）。电压存储电路包括单位增益放大器（UGA）和第一，第二和第三开关。第一个开关连接UGA的输入端和VCO的输入端，以便在PLL从RUN模式转换到STOP模式之前对控制电压进行采样。当PLL处于STOP模式时，第二个开关连接UGA的输入和输出端，以存储采样的控制电压。当PLL从STOP模式转换到RUN模式时，第三个开关将UGA的输出端连接到低通滤波器（LPF）的输入端，以将存储的控制电压提供给LPF。

4. 发明授权

US08689023B2 Digital logic controller for regulating voltage of a system on chip 有权
标题翻译：用于调节片上系统电压的数字逻辑控制器
公开(公告)号：US08689023B2
公开(公告)日：2014-04-01
申请号：US13275310
申请日：2011-10-17
申请人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
发明人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
IPC分类号： G06F1/00
CPC分类号： G05F1/575
摘要： A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.
摘要翻译：用于调节SoC的电压的数字逻辑控制器包括用于接收具有在SoC的工作条件范围内恒定的第一特性的参考信号的第一输入端和用于接收第二信号的第二输入端表示SoC的运行状况的属性。第二个属性可能在SoC的一系列操作条件下变化。比较器比较第一和第二特性和数字逻辑控制器，基于该比较，输出到调节信号到电压调节器，以调节在目标电压或其附近的目标电压的电压，该目标电压高于最低工作电压 SoC。

5. 发明申请

US20130265094A1 LEVEL SHIFTER CIRCUIT 审中-公开
标题翻译：水平更换电路
公开(公告)号：US20130265094A1
公开(公告)日：2013-10-10
申请号：US13439858
申请日：2012-04-05
申请人： Samaksh Sinha , Sunny Gupta
发明人： Samaksh Sinha , Sunny Gupta
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： A level shifter circuit for shifting voltage level of an input signal includes a supply voltage generation circuit, an inverter, and a cross-coupled latch. The supply voltage generation circuit generates a low-voltage supply using a high-voltage supply. The low-voltage supply is used by the inverter to generate an inverted input signal. The input signal and the inverted input signal are provided to the cross-coupled latch, which generates a level shifted output signal.
摘要翻译：用于移位输入信号的电压电平的电平移位器电路包括电源电压产生电路，反相器和交叉耦合的锁存器。供电电压产生电路使用高压电源产生低压电源。变频器使用低压电源产生反相输入信号。输入信号和反相输入信号被提供给交叉耦合的锁存器，其产生电平移位的输出信号。

6. 发明申请

US20130339761A1 POWER MANAGEMENT SYSTEM FOR ELECTRONIC CIRCUIT 有权
标题翻译：电子电路电源管理系统
公开(公告)号：US20130339761A1
公开(公告)日：2013-12-19
申请号：US13525347
申请日：2012-06-17
申请人： Kumar Abhishek , Manmohan Rana , Samaksh Sinha
发明人： Kumar Abhishek , Manmohan Rana , Samaksh Sinha
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/3243 , H02J1/08 , H02J9/005 , H02J2001/008 , Y02D10/152 , Y02D50/20
摘要： A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal.
摘要翻译：一种用于管理由核心电源供应到电子电路的电力的电源管理电路。电子电路包括数字和模拟电路域，并在POWER-ON，RUN和STANDBY模式下工作。电源管理电路包括主状态机，其与模拟电路域交换握手信号以监视操作模式并产生第一和第二配置信号。电源管理电路基于第一和第二配置信号启用和禁用模拟电路域。连接到核心电源和数字电路模块的开关基于第二配置信号启用和禁用数字电路域。

7. 发明授权

US08890602B2 Well-biasing circuit for integrated circuit 有权
标题翻译：集成电路的良好偏置电路
公开(公告)号：US08890602B2
公开(公告)日：2014-11-18
申请号：US13743324
申请日：2013-01-16
申请人： Samaksh Sinha , Manmohan Rana , Nishant Singh Thakur
发明人： Samaksh Sinha , Manmohan Rana , Nishant Singh Thakur
IPC分类号： H03K3/01
CPC分类号： G05F3/02 , G05F3/205
摘要： A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
摘要翻译：用于集成电路（IC）的阱偏置电路包括用于向阱偏压触点（n阱和p阱偏压触点）提供良好偏置电压（n阱和p阱偏置电压）的阱偏压调节器）当集成电路处于STOP和STANDBY模式时，IC的每个单元格。在IC处于RUN和STOP模式和STANDBY模式时，开关连接在核心电源和阱偏压触点之间，用于连接和断开芯电源和阱偏压触点。分别在IC处于RUN模式和STOP和STANDBY模式时，电压反相器电路和CMOS反相电路使能和禁止开关。

8. 发明授权

US08762753B2 Power management circuit using two configuration signals to control the power modes of two circuit modules using two crosslinked multiplexers and a level shifter 有权
标题翻译：电源管理电路使用两个配置信号来控制两个电路模块的功率模式，使用两个交流多路复用器和电平转换器
公开(公告)号：US08762753B2
公开(公告)日：2014-06-24
申请号：US13525347
申请日：2012-06-17
申请人： Kumar Abhishek , Manmohan Rana , Samaksh Sinha
发明人： Kumar Abhishek , Manmohan Rana , Samaksh Sinha
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/3243 , H02J1/08 , H02J9/005 , H02J2001/008 , Y02D10/152 , Y02D50/20
摘要： A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal.
摘要翻译：一种用于管理由核心电源供应到电子电路的电力的电源管理电路。电子电路包括数字和模拟电路域，并在POWER-ON，RUN和STANDBY模式下工作。电源管理电路包括主状态机，其与模拟电路域交换握手信号以监视操作模式并产生第一和第二配置信号。电源管理电路基于第一和第二配置信号启用和禁用模拟电路域。连接到核心电源和数字电路模块的开关基于第二配置信号启用和禁用数字电路域。

9. 发明申请

US20130286751A1 BUFFER AND CONTROL CIRCUIT FOR SYNCHRONOUS MEMORY CONTROLLER 有权
标题翻译：同步存储器控制器的缓冲器和控制电路
公开(公告)号：US20130286751A1
公开(公告)日：2013-10-31
申请号：US13456217
申请日：2012-04-26
申请人： Nitin Pant , Trong D. Nguyen , Samaksh Sinha
发明人： Nitin Pant , Trong D. Nguyen , Samaksh Sinha
IPC分类号： G11C7/10 , H03K5/22
CPC分类号： H03K5/2481
摘要： A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.
摘要翻译：用于同步存储器控制器的缓冲器和控制电路包括第一和第二差分比较器和控制逻辑。第一差分比较器具有正差分输入信号和负差分输入信号，第二差分比较器具有偏移正差分输入信号和负差分输入信号。第一和第二差分比较器基于正和负差分输入信号的幅度以及偏移的正和负差分输入信号产生输出信号。控制逻辑基于输出信号产生参考选通信号。

10. 发明申请

US20140197883A1 WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT 有权
标题翻译：集成电路的全自动电路
公开(公告)号：US20140197883A1
公开(公告)日：2014-07-17
申请号：US13743324
申请日：2013-01-16
申请人： Samaksh Sinha , Manmohan Rana , Nishant Singh Thakur
发明人： Samaksh Sinha , Manmohan Rana , Nishant Singh Thakur
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , G05F3/205
摘要： A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
摘要翻译：用于集成电路（IC）的阱偏置电路包括用于向阱偏压触点（n阱和p阱偏压触点）提供良好偏置电压（n阱和p阱偏置电压）的阱偏压调节器）当集成电路处于STOP和STANDBY模式时，IC的每个单元格。在IC处于RUN和STOP模式和STANDBY模式时，开关连接在核心电源和阱偏压触点之间，用于连接和断开芯电源和阱偏压触点。分别在IC处于RUN模式和STOP和STANDBY模式时，电压反相器电路和CMOS反相电路使能和禁止开关。

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