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1. 发明申请

US20100322004A1 SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD IN THE SAME 失效
标题翻译：半导体存储器件及其擦除方法
公开(公告)号：US20100322004A1
公开(公告)日：2010-12-23
申请号：US12871758
申请日：2010-08-30
申请人： Sam Kyu WON , Jae Won Cha , In Ho Kang , Kwang Ho Baek
发明人： Sam Kyu WON , Jae Won Cha , In Ho Kang , Kwang Ho Baek
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/3404 , G11C16/344
摘要： A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.
摘要翻译：公开了一种半导体存储器件及其擦除方法。半导体存储器件包括配置成具有存储单元耦合的单元串的存储单元阵列，被配置为切换存储单元阵列的全局字线和字线的块开关，被配置为控制该块的块解码器开关和被配置为使用充电在存储单元阵列的P阱中的擦除电压作为块解码器的电源电压的再循环开关。

2. 发明申请

US20090231919A1 SEMICONDUCTOR MEMORY DEVICE AND ERASE METHOD IN THE SAME 失效
标题翻译：半导体存储器件及其擦除方法
公开(公告)号：US20090231919A1
公开(公告)日：2009-09-17
申请号：US12136738
申请日：2008-06-10
申请人： Sam Kyu WON , Jae Won Cha , In Ho Kang , Kwang Ho Baek
发明人： Sam Kyu WON , Jae Won Cha , In Ho Kang , Kwang Ho Baek
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/3404 , G11C16/344
摘要： A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.
摘要翻译：公开了一种半导体存储器件及其擦除方法。半导体存储器件包括配置成具有存储单元耦合的单元串的存储单元阵列，被配置为切换存储单元阵列的全局字线和字线的块开关，被配置为控制该块的块解码器开关和被配置为使用充电在存储单元阵列的P阱中的擦除电压作为块解码器的电源电压的再循环开关。

3. 发明申请

US20090067254A1 NON-VOLATILE MEMORY DEVICE AND A METHOD OF PROGRAMMING A MULTI LEVEL CELL IN THE SAME 有权
标题翻译：非易失性存储器件和一种编程其中的多级电池的方法
公开(公告)号：US20090067254A1
公开(公告)日：2009-03-12
申请号：US12019929
申请日：2008-01-25
申请人： Sam Kyu WON , Jae Won Cha , Kwang Ho Baek
发明人： Sam Kyu WON , Jae Won Cha , Kwang Ho Baek
IPC分类号： G11C16/34
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator cell. A first verifying operation is performed based on a first verifying voltage of the main cell and the indicator cell. The program operation and the first verifying operation are performed repeatedly until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage. A second verifying operation is performed on the main cell based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.
摘要翻译：在非易失性存储器件中编程多级单元的方法包括向主单元和指示单元提供不同的数据。主电池和指示电池根据数据具有不同的阈值电压。在主单元和指示单元上执行程序操作。基于主单元和指示单元的第一验证电压执行第一验证操作。重复执行编程操作和第一验证操作，直到指示单元的第一单元的阈值电压高于第一验证电压。当第一单元的阈值电压高于第一验证电压时，基于第二验证电压在主单元上执行第二验证操作。

4. 发明申请

US20110026325A1 METHOD OF PROGRAMMING A MULTI LEVEL CELL 有权
标题翻译：编程多级细胞的方法
公开(公告)号：US20110026325A1
公开(公告)日：2011-02-03
申请号：US12902102
申请日：2010-10-11
申请人： Sam Kyu WON , Jae Won Cha , Kwang Ho Baek
发明人： Sam Kyu WON , Jae Won Cha , Kwang Ho Baek
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.
摘要翻译：一种对非易失性存储器件中的多级单元进行编程的方法包括：对主单元和指示单元执行程序操作; 基于第一验证电压对主单元和指示单元执行第一验证操作; 重复执行编程操作和第一验证操作，直到指示单元的第一单元的阈值电压高于第一验证电压; 以及当所述第一单元的阈值电压高于所述第一验证电压时，基于所述第二验证电压对所述主单元和所述指示单元执行第二验证操作。

5. 发明申请

US20090141551A1 METHOD FOR PERFORMING ERASING OPERATION IN NONVOLATILE MEMORY DEVICE 有权
标题翻译：在非易失性存储器件中执行擦除操作的方法
公开(公告)号：US20090141551A1
公开(公告)日：2009-06-04
申请号：US12135835
申请日：2008-06-09
申请人： Sam Kyu WON , Jae Won Cha , Kwang Ho Baek
发明人： Sam Kyu WON , Jae Won Cha , Kwang Ho Baek
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/16
摘要： A method for performing erasing operation in a nonvolatile memory device includes the steps of applying an erasing voltage to P-wells of a selected memory cell block which is composed of a plurality of strings in each of which a plurality of memory cells and side memory cells are connected in series; performing soft programming operation by applying a soft programming voltage to word lines of the selected memory cell block; and programming the side memory cells by applying a programming voltage to the side memory cells.
摘要翻译：一种在非易失性存储器件中执行擦除操作的方法包括以下步骤：将擦除电压施加到由多个存储单元和侧存储单元组成的多个串组成的所选存储单元块的P阱中串联连接通过对所选存储单元块的字线施加软编程电压来执行软编程操作; 以及通过向侧面存储器单元施加编程电压来对侧面存储器单元进行编程。

6. 发明申请

US20090040830A1 BLOCK DECODER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：块解码器和半导体存储器件，包括它们
公开(公告)号：US20090040830A1
公开(公告)日：2009-02-12
申请号：US12163905
申请日：2008-06-27
申请人： Kwang Ho BAEK , Sam Kyu WON , Jae Won CHA
发明人： Kwang Ho BAEK , Sam Kyu WON , Jae Won CHA
IPC分类号： G11C16/04 , G11C7/00 , G11C8/00
CPC分类号： G11C16/08 , G11C11/10 , G11C11/12 , G11C11/14 , G11C16/0483
摘要： A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal.
摘要翻译：半导体存储器件可以通过阻止流过存储单元的泄漏电流来改善电性能，以便当非选择存储单元块的漏极选择晶体管，源选择晶体管和侧晶体管截止时半导体存储器件工作。半导体存储器件包括存储单元块，其中多个存储器单元，漏极和源极选择晶体管和侧面字线晶体管串联连接在一起;块解码器，用于响应于预解码的地址信号输出块选择信号以及控制漏极和源极选择晶体管和侧面字线晶体管，以及用于响应于块选择信号将全局字线连接到存储器单元块的字线的块开关。

7. 发明申请

US20100046293A1 MEMORY CELL BLOCK OF NONVOLATILE MEMORY DEVICE AND METHOD OF MANAGING SUPPLEMENTARY INFORMATION 审中-公开
标题翻译：非易失性存储器件的存储单元块和管理补充信息的方法
公开(公告)号：US20100046293A1
公开(公告)日：2010-02-25
申请号：US12493335
申请日：2009-06-29
申请人： Sam Kyu WON
发明人： Sam Kyu WON
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427 , G11C16/3436 , G11C29/028 , G11C29/50
摘要： A nonvolatile memory device of a nonvolatile memory device includes a memory cell unit comprising sets of memory cells, a first supplementary information repository comprising source-side dummy cells respectively connected between source select transistors and first memory cells of the sets of the memory cells, and a second supplementary information repository comprising drain-side dummy cells respectively connected between drain select transistors and second memory cells of the sets of the memory cells.
摘要翻译：非易失性存储器件的非易失性存储器件包括存储单元单元，其包括存储单元组，第一补充信息库，其包括分别连接在所述存储单元组的源选择晶体管和第一存储单元之间的源极虚拟单元，以及第二补充信息库，其包括分别连接在所述存储单元组的漏极选择晶体管和第二存储器单元之间的漏极侧虚设单元。

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