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1. 发明授权

US07302553B2 Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue 有权
标题翻译：用于快速确定非移动指令队列中最旧指令的装置，系统和方法
公开(公告)号：US07302553B2
公开(公告)日：2007-11-27
申请号：US10351556
申请日：2003-01-23
申请人： Sam Gat-Shang Chu , Hung Qui Le , Dung Quoc Nguyen
发明人： Sam Gat-Shang Chu , Hung Qui Le , Dung Quoc Nguyen
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the instructions in the queue is recorded. Using the present status of the instructions in the queue in conjunction with previously recorded statuses of the instructions, the oldest instruction in the queue is determined. The status of the instructions in the queue includes whether or not the instruction has been issued for execution as well as whether or not it is known that the issued instruction has been accepted for execution.
摘要翻译：提供了一种用于快速确定处理器的非移动指令队列中的最旧指令的装置，系统和方法。特别地，在不移动队列中，以时钟周期一次存储指令。在每个时钟周期，记录队列中的指令的当前状态。结合队列中的指令的当前状态结合先前记录的指令状态，确定队列中最早的指令。队列中的指令的状态包括是否已经发出指令执行，以及是否知道发出的指令已被接受执行。

2. 发明授权

US07663963B2 Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array 有权
标题翻译：使用2Read / 2Write寄存器文件阵列提供多次读/写的装置和方法
公开(公告)号：US07663963B2
公开(公告)日：2010-02-16
申请号：US12134537
申请日：2008-06-06
申请人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Dung Quoc Nguyen , Jafar Nahidi
发明人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Dung Quoc Nguyen , Jafar Nahidi
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译：提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。两条读字线用于访问子阵列中条目的两个读端口。

3. 发明申请

US20080239860A1 Apparatus and Method for Providing Multiple Reads/Writes Using a 2Read/2Write Register File Array 有权
标题翻译：使用2Read / 2Write寄存器文件阵列提供多个读/写的装置和方法
公开(公告)号：US20080239860A1
公开(公告)日：2008-10-02
申请号：US12134537
申请日：2008-06-06
申请人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Dung Quoc Nguyen , Jafar Nahidi
发明人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Dung Quoc Nguyen , Jafar Nahidi
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译：提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。两条读字线用于访问子阵列中条目的两个读端口。

4. 发明授权

US07243209B2 Apparatus and method for speeding up access time of a large register file with wrap capability 有权
标题翻译：用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法
公开(公告)号：US07243209B2
公开(公告)日：2007-07-10
申请号：US11044449
申请日：2005-01-27
申请人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Jafar Nahidi , Dung Quoc Nguyen
发明人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Jafar Nahidi , Dung Quoc Nguyen
IPC分类号： G06F9/34 , G06F13/00
CPC分类号： G06F9/30141 , G06F9/30098
摘要： An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
摘要翻译：提供了一种用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法。利用该装置和方法，从电路配置中消除了传统寄存器文件系统中的2：1多路复用器，而是提供了一半地址的附加主复用器，例如寄存器堆的前四个子阵列，需要包装能力。这些附加的主多路复用器接收读地址和移位的读字线信号。另一个主复用器接收读地址和未移位的读字线信号。来自移位和未移位的主复用器的输出被提供给一组次级多路复用器，它们将来自移位和未移位的主复用器的输出的比特复用以产生要由多个读/写寄存器堆使用的读地址系统。

5. 发明授权

US07400548B2 Method for providing multiple reads/writes using a 2read/2write register file array 有权
标题翻译：使用2read / 2write寄存器文件阵列提供多次读/写的方法
公开(公告)号：US07400548B2
公开(公告)日：2008-07-15
申请号：US11054276
申请日：2005-02-09
申请人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Dung Quoc Nguyen , Jafar Nahidi
发明人： Sam Gat-Shang Chu , Maureen Anne Delaney , Saiful Islam , Dung Quoc Nguyen , Jafar Nahidi
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译：提供了使用2Read / 2Write寄存器文件读取多个连续条目并且仅写入一个读取地址和一个写入地址的多个连续条目。在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。还提供了通过仅对一个地址进行4至16个解码来写入连续条目的机制。此外，提供了一种用于使用起始读取字地址和基于起始读取字地址生成的两个读取字线从寄存器堆栈数据读取数据的机制。两条读字线用于访问子阵列中条目的两个读端口。

6. 发明授权

US08418180B2 Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先级方法，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US08418180B2
公开(公告)日：2013-04-09
申请号：US12129876
申请日：2008-05-30
申请人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
发明人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

7. 发明申请

US20090063898A1 Processor Instruction Retry Recovery 失效
标题翻译：处理器指令重试恢复
公开(公告)号：US20090063898A1
公开(公告)日：2009-03-05
申请号：US12270300
申请日：2008-11-13
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/20
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

8. 发明授权

US07490226B2 Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor 失效
标题翻译：使用包括第一和第二位的矢量分量来调节微处理器中相关指令的移动的方法
公开(公告)号：US07490226B2
公开(公告)日：2009-02-10
申请号：US11054289
申请日：2005-02-09
申请人： Hung Qui Le , Dung Quoc Nguyen , Raymond Cheung Yeung
发明人： Hung Qui Le , Dung Quoc Nguyen , Raymond Cheung Yeung
IPC分类号： G06F9/312
CPC分类号： G06F9/383 , G06F9/3834 , G06F9/3838 , G06F9/3867
摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.
摘要翻译：提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器阶段。

9. 发明授权

US07467325B2 Processor instruction retry recovery 有权
标题翻译：处理器指令重试恢复
公开(公告)号：US07467325B2
公开(公告)日：2008-12-16
申请号：US11055258
申请日：2005-02-10
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

10. 发明申请

US20080222395A1 System and Method for Predictive Early Allocation of Stores in a Microprocessor 失效
标题翻译：微处理器中商店预测性早期分配的系统和方法
公开(公告)号：US20080222395A1
公开(公告)日：2008-09-11
申请号：US11683843
申请日：2007-03-08
申请人： Hung Qui Le , Dung Quoc Nguyen
发明人： Hung Qui Le , Dung Quoc Nguyen
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3857 , G06F9/3859
摘要： A system and method for predictive early allocation of stores in a microprocessor is presented. During instruction dispatch, an instruction dispatch unit retrieves an instruction from an instruction cache (Icache). When the retrieved instruction is an interruptible instruction, the instruction dispatch unit loads the interruptible instruction's instruction tag (IITAG) into an interruptible instruction tag register. A load store unit loads subsequent instruction information (instruction tag and store data) along with the interruptible instruction tag in a store data queue entry. Comparison logic receives a completing instruction tag from completion logic, and compares the completing instruction tag with the interruptible instruction tags included in the store data queue entries. In turn, deallocation logic deallocates those store data queue entries that include an interruptible instruction tag that matches the completing instruction tag.
摘要翻译：提出了一种用于在微处理器中预先提前存储分配的系统和方法。在指令调度期间，指令调度单元从指令高速缓存（Icache）检索指令。当检索到的指令是可中断指令时，指令调度单元将可中断指令的指令标记（IITAG）加载到可中断指令标记寄存器中。加载存储单元将后续指令信息（指令标签和存储数据）与可中断指令标签一起存储在存储数据队列条目中。比较逻辑从完成逻辑接收完成指令标记，并将完成指令标签与包含在存储数据队列条目中的可中断指令标签进行比较。反过来，解配分配逻辑会释放那些包含与完成指令标记匹配的可中断指令标签的存储数据队列条目。

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