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1. 发明申请

US20170140939A1 PROCESS OF FORMING SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20170140939A1
公开(公告)日：2017-05-18
申请号：US15352811
申请日：2016-11-16
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Yasuyo Kurachi
IPC分类号： H01L21/265 , H01L29/20 , H01L29/205 , H01L29/778 , H01L23/544 , H01L21/311 , H01L21/02 , H01L21/78 , H01L21/324 , H01L29/06 , H01L29/66
CPC分类号： H01L21/2654 , H01L21/0217 , H01L21/0254 , H01L21/31116 , H01L21/3245 , H01L21/78 , H01L23/544 , H01L29/0653 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L2223/5446
摘要： A process of forming a semiconductor device using plasma processes is disclosed. The semiconductor device includes a device area, a scribed area, and a peripheral area on a wafer, where these areas have respective conductive regions. The process includes steps of (a) implanting ions to isolate the conductive regions in the device area from the conductive region in the scribed area; (b) forming a metal film so as to cover a back surface, a side, and the peripheral area in the top surface of the wafer; (c) deposing insulating film on a whole surface of the wafer; and (d) selectively etching, by the plasma process, the insulating film so as to expose the conductive regions in the device area and the scribed area. During the plasma process, the metal film in the back surface of the wafer is connected the apparatus ground that effectively dissipates charges induced by the plasm to the apparatus ground through the metal film.

2. 发明申请

US20130256752A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130256752A1
公开(公告)日：2013-10-03
申请号：US13853748
申请日：2013-03-29
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Yasuyo Kurachi
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L29/205 , H01L29/452 , H01L29/66462 , H01L29/7785
摘要： A semiconductor device includes: an operation layer that is provided on a substrate and is made of a GaAs-based semiconductor; a first AlGaAs layer provided on the operation layer; a gate electrode provided on the first AlGaAs layer; an second AlGaAs layer having n-type conductivity and provided on the first AlGaAs layer of both sides of the gate electrode, an Al composition ratio of the second AlGaAs layer being larger than that of the first AlGaAs layer and being equal to or more than 0.3 and equal to or less than 0.5; an n-type GaAs layer selectively provided on the second AlGaAs layer; and a source electrode and a drain electrode that contain Au and are provided on the n-type GaAs layer.
摘要翻译：半导体器件包括：工作层，其设置在基板上并由GaAs类半导体制成; 设置在操作层上的第一AlGaAs层; 设置在所述第一AlGaAs层上的栅电极; 具有n型导电性的第二AlGaAs层，并且设置在栅电极两侧的第一AlGaAs层上，第二AlGaAs层的Al组成比大于第一AlGaAs层的Al组成比，并且等于或大于0.3 并且等于或小于0.5; 选择性地设置在第二AlGaAs层上的n型GaAs层; 以及包含Au并且设置在n型GaAs层上的源电极和漏电极。

3. 发明授权

US10283585B2 Process of forming capacitor 有权
公开(公告)号：US10283585B2
公开(公告)日：2019-05-07
申请号：US15641681
申请日：2017-07-05
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Yasuyo Kurachi , Takeshi Igarashi
IPC分类号： H01L49/02 , H01L21/768
摘要： A process of forming a metal-insulator-metal (MIM) capacitor is disclosed. The process includes steps of (i) forming an insulating film as a dielectric film of the MIM capacitor; (ii) forming a first portion of an upper electrode by a metal evaporation and a lift-off technique subsequent to the metal evaporation; and (iii) forming a second portion of the upper electrode by the metal evaporation and the lift-off technique subsequent to the metal evaporation for the second portion.

4. 发明授权

US09960043B2 Process of forming semiconductor device 有权
公开(公告)号：US09960043B2
公开(公告)日：2018-05-01
申请号：US15352811
申请日：2016-11-16
申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
发明人： Yasuyo Kurachi
IPC分类号： H01L21/265 , H01L21/311 , H01L21/78 , H01L29/778 , H01L29/06 , H01L29/20 , H01L29/205 , H01L29/66 , H01L21/02 , H01L21/324 , H01L23/544
CPC分类号： H01L21/2654 , H01L21/0217 , H01L21/0254 , H01L21/31116 , H01L21/3245 , H01L21/78 , H01L23/544 , H01L29/0653 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L2223/5446
摘要： A process of forming a semiconductor device using plasma processes is disclosed. The semiconductor device includes a device area, a scribed area, and a peripheral area on a wafer, where these areas have respective conductive regions. The process includes steps of (a) implanting ions to isolate the conductive regions in the device area from the conductive region in the scribed area; (b) forming a metal film so as to cover a back surface, a side, and the peripheral area in the top surface of the wafer; (c) deposing insulating film on a whole surface of the wafer; and (d) selectively etching, by the plasma process, the insulating film so as to expose the conductive regions in the device area and the scribed area. During the plasma process, the metal film in the back surface of the wafer is connected the apparatus ground that effectively dissipates charges induced by the plasm to the apparatus ground through the metal film.

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