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1. 发明授权

US09117805B2 Air-spacer MOS transistor 有权
标题翻译：空气隔离MOS晶体管
公开(公告)号：US09117805B2
公开(公告)日：2015-08-25
申请号：US14169913
申请日：2014-01-31
申请人： STMicroelectronics S.A. , STMicroelectronics (Crolles 2) SAS , Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Heimanu Niebojewski , Yves Morand , Cyrille Le Royer
IPC分类号： H01L29/66 , H01L21/28 , H01L29/49 , H01L29/423
CPC分类号： H01L29/49 , H01L21/28008 , H01L21/28114 , H01L29/42376 , H01L29/4925 , H01L29/4991 , H01L29/6653
摘要： A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.
摘要翻译：一种MOS晶体管，包括在栅极绝缘体上方的具有高度，长度和宽度的导电栅极堆叠，该堆叠具有靠近栅绝缘体的下部和上部，其中堆叠具有第一长度下部，并且在其上部比第一长度短的第二长度。

2. 发明授权

US08822332B2 Method for forming gate, source, and drain contacts on a MOS transistor 有权
标题翻译：在MOS晶体管上形成栅极，源极和漏极接触的方法
公开(公告)号：US08822332B2
公开(公告)日：2014-09-02
申请号：US13871884
申请日：2013-04-26
申请人： STMicroelectronics S.A. , Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Heimanu Niebojewski , Yves Morand , Cyrille Le Royer , Fabrice Nemouchi
IPC分类号： H01L21/311 , H01L21/28 , H01L29/66 , H01L21/768
CPC分类号： H01L29/66477 , H01L21/28247 , H01L21/76897 , H01L21/823425 , H01L21/823443 , H01L21/823475 , H01L21/84 , H01L29/66545 , H01L29/66606
摘要： A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.
摘要翻译：一种用于在MOS晶体管上形成栅极，源极和漏极接触的方法，其具有包括被金属栅极硅化物覆盖的多晶硅的绝缘栅极，该栅极由至少一个由第一绝缘材料制成的隔离物包围，该方法包括以下步骤： a）用第二绝缘材料覆盖结构并使第二绝缘材料平整以到达栅极硅化物; b）氧化栅极，使得栅极硅化物掩埋并覆盖氧化硅; c）选择性地去除所述第二绝缘材料; 以及d）用第一导电材料覆盖所述结构，并且将所述第一导电材料一直调整到所述隔离物顶部的较低水平。

3. 发明授权

US09252269B2 Tunnel effect transistor 有权
标题翻译：隧道效应晶体管
公开(公告)号：US09252269B2
公开(公告)日：2016-02-02
申请号：US14199501
申请日：2014-03-06
申请人： Commissariat à l'énergie atomique et aux énergies alternatives
发明人： Costin Anghel , Cyrille Le Royer , Adam Makosiej
IPC分类号： H01L29/78 , H01L29/739 , H01L29/06 , H01L29/417
CPC分类号： H01L29/7833 , H01L29/0657 , H01L29/41775 , H01L29/7391
摘要： A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region.
摘要翻译：隧道效应晶体管包括由本征半导体材料制成的沟道; 源极和漏极延伸区域，源极延伸区域由根据第一类型的掺杂P或N掺杂的半导体材料制成，并且漏极延伸区域由根据第二类型掺杂的半导体材料制成的掺杂与所述第一类掺杂相反; 源极和漏极导电区域分别与源极和漏极延伸区域接触; 栅极结构，包括与沟道接触的栅极电介质层和栅极区域，栅极介质层布置在栅极区域和沟道之间; 以及根据插入在沟道和漏极延伸区域之间的第一类型的掺杂掺杂的区域。

4. 发明申请

US20140252407A1 TUNNEL EFFECT TRANSISTOR 有权
标题翻译：隧道效应晶体管
公开(公告)号：US20140252407A1
公开(公告)日：2014-09-11
申请号：US14199501
申请日：2014-03-06
申请人： Commissariat à l'énergie atomique et aux énergies alternatives
发明人： Costin Anghel , Cyrille Le Royer , Adam Makosiej
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L29/0657 , H01L29/41775 , H01L29/7391
摘要： A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region.
摘要翻译：隧道效应晶体管包括由本征半导体材料制成的沟道; 源极和漏极延伸区域，源极延伸区域由根据第一类型的掺杂P或N掺杂的半导体材料制成，并且漏极延伸区域由根据第二类型掺杂的半导体材料制成的掺杂与所述第一类掺杂相反; 源极和漏极导电区域分别与源极和漏极延伸区域接触; 栅极结构，包括与沟道接触的栅极电介质层和栅极区域，栅极介质层布置在栅极区域和沟道之间; 以及根据插入在沟道和漏极延伸区域之间的第一类型的掺杂掺杂的区域。

5. 发明申请

US20140217520A1 AIR-SPACER MOS TRANSISTOR 有权
标题翻译：空气离子MOS晶体管
公开(公告)号：US20140217520A1
公开(公告)日：2014-08-07
申请号：US14169913
申请日：2014-01-31
申请人： STMicroelectronics S.A. , STMicroelectronics (Crolles 2) SAS , Commissariat à I'Énergie Atomique et aux Énergies Alternatives
发明人： Heimanu Niebojewski , Yves Morand , Cyrille Le Royer
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/49 , H01L21/28008 , H01L21/28114 , H01L29/42376 , H01L29/4925 , H01L29/4991 , H01L29/6653
摘要： A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.
摘要翻译：一种MOS晶体管，包括在栅极绝缘体上方的具有高度，长度和宽度的导电栅极堆叠，该堆叠具有靠近栅绝缘体的下部和上部，其中堆叠具有第一长度下部，并且在其上部比第一长度短的第二长度。

6. 发明授权

US09502558B2 Local strain generation in an SOI substrate 有权
标题翻译： SOI衬底中的局部应变产生
公开(公告)号：US09502558B2
公开(公告)日：2016-11-22
申请号：US14791713
申请日：2015-07-06
申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives , STMICROELECTRONICS (CROLLES 2) SAS
发明人： Shay Reboh , Laurent Grenouillet , Cyrille Le Royer , Sylvain Maitrejean , Yves Morand
IPC分类号： H01L29/78 , H01L21/02 , H01L21/265 , H01L29/66
CPC分类号： H01L29/7847 , H01L21/02532 , H01L21/02592 , H01L21/02667 , H01L21/26506 , H01L29/66477 , H01L29/66772 , H01L29/7849
摘要： Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphized, before the transistor gate is made.
摘要翻译：使用在晶体管栅极制造之前利用其中位于衬底（图6）的绝缘层下方的区域非晶化的SMT应力存储技术的半导体绝缘体型晶体管的晶体管的沟道区域的方法。

7. 发明授权

US09911820B2 Method for fabrication of a field-effect with reduced stray capacitance 有权
公开(公告)号：US09911820B2
公开(公告)日：2018-03-06
申请号：US15464763
申请日：2017-03-21
申请人： Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
发明人： Cyrille Le Royer , Frederic Boeuf , Laurent Grenouillet , Louis Hutin , Yves Morand
IPC分类号： H01L29/06 , H01L29/49 , H01L29/51 , H01L23/535 , H01L29/66 , H01L21/768
CPC分类号： H01L29/4983 , H01L21/76895 , H01L23/535 , H01L29/0649 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/66628
摘要： A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

8. 发明申请

US20150091089A1 AIR-SPACER MOS TRANSISTOR 审中-公开
标题翻译：空气离子MOS晶体管
公开(公告)号：US20150091089A1
公开(公告)日：2015-04-02
申请号：US14499545
申请日：2014-09-29
申请人： STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS SA , Commissariat A L'Energie Atomique et aux Energies Alternatives
发明人： Heimanu Niebojewski , Yves Morand , Cyrille Le Royer , Olivier Rozeau
IPC分类号： H01L29/51 , H01L29/66 , H01L29/08 , H01L29/78
CPC分类号： H01L29/515 , H01L29/0843 , H01L29/4983 , H01L29/4991 , H01L29/51 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/78
摘要： A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers.
摘要翻译： MOS晶体管具有由沉积在衬底上的高介电常数材料制成的栅极绝缘体层。栅极绝缘体层以恒定的厚度延伸到栅极堆叠之下和之外。通过栅极绝缘体层的延伸超过栅极叠层的侧面，在栅极叠层的任一侧上形成具有低介电常数的隔板并与衬底垂直分离。低介电常数的间隔物优选为空气间隔物。

9. 发明申请

US20130295734A1 METHOD FOR FORMING GATE, SOURCE, AND DRAIN CONTACTS ON A MOS TRANSISTOR 有权
标题翻译：在MOS晶体管上形成栅极，源极和漏极触点的方法
公开(公告)号：US20130295734A1
公开(公告)日：2013-11-07
申请号：US13871884
申请日：2013-04-26
申请人： STMicroelectronics S.A. , Commissariat a l'Energie Atomique et aux Energies Alternatives
发明人： Heimanu Niebojewski , Yves Morand , Cyrille Le Royer , Fabrice Nemouchi
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/28247 , H01L21/76897 , H01L21/823425 , H01L21/823443 , H01L21/823475 , H01L21/84 , H01L29/66545 , H01L29/66606
摘要： A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.
摘要翻译：一种用于在MOS晶体管上形成栅极，源极和漏极接触的方法，其具有包括被金属栅极硅化物覆盖的多晶硅的绝缘栅极，该栅极由至少一个由第一绝缘材料制成的隔离物包围，该方法包括以下步骤： a）用第二绝缘材料覆盖结构并使第二绝缘材料平整以到达栅极硅化物; b）氧化栅极，使得栅极硅化物掩埋并覆盖氧化硅; c）选择性地去除所述第二绝缘材料; 以及d）用第一导电材料覆盖所述结构，并且将所述第一导电材料一直调整到所述隔离物顶部的较低水平。

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