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1. 发明授权

US10193506B2 Methods and circuits to reduce pop noise in an audio device 有权
公开(公告)号：US10193506B2
公开(公告)日：2019-01-29
申请号：US15377929
申请日：2016-12-13
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03F1/32 , H03G3/34 , H03F3/45 , H03F3/187 , H03F3/217 , H03F1/02 , H04R3/00 , H03F1/30 , H03F3/183 , H03F3/185 , H03F3/21
摘要： A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

2. 发明申请

US20170093348A1 METHODS AND CIRCUITS TO REDUCE POP NOISE IN AN AUDIO DEVICE 审中-公开
公开(公告)号：US20170093348A1
公开(公告)日：2017-03-30
申请号：US15377929
申请日：2016-12-13
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03F1/32 , H03G3/34 , H03F3/45 , H03F3/187 , H03F3/217
CPC分类号： H03F1/3205 , H03F1/0205 , H03F1/305 , H03F3/183 , H03F3/185 , H03F3/187 , H03F3/211 , H03F3/2171 , H03F3/2173 , H03F3/45179 , H03F2200/03 , H03F2200/351 , H03F2203/21106 , H03F2203/45151 , H03F2203/45156 , H03G3/345 , H03G3/348 , H04R3/002
摘要： A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

3. 发明申请

US20160329868A1 HIGH EFFICIENCY CLASS D AMPLIFIER WITH REDUCED GENERATION OF EMI 有权
标题翻译：具有降低EMI产生的高效级D放大器
公开(公告)号：US20160329868A1
公开(公告)日：2016-11-10
申请号：US14715879
申请日：2015-05-19
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd
发明人： Qi Yu Liu , Hong Wu Lin
IPC分类号： H03F3/217 , H03F3/45 , H03F3/183
CPC分类号： H03F3/183 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/03 , H03F2203/45138
摘要： A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.
摘要翻译： D类放大器包括信号处理块。当第一差分信号的占空比大于第二差分信号的占空比时，信号处理块产生表示第一差分信号和第二差分信号之间的差的第一处理信号。当第一差分信号的占空比小于第二差分信号的占空比时，信号处理块产生表示参考DC电平的第一处理信号。当第二差分信号的占空比大于第一差分信号的占空比时，产生表示第二差分信号和第一差分信号之间的差的第二处理信号，并且生成表示参考DC电平的第二处理信号当第二差分信号的占空比小于第一差分信号的占空比时。

4. 发明授权

US11750163B2 Deglitching circuit and method in a class-D amplifier 有权
公开(公告)号：US11750163B2
公开(公告)日：2023-09-05
申请号：US17200490
申请日：2021-03-12
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd.
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03F3/217 , H03G1/04 , H03K19/017 , H03K19/20 , H03K19/003 , H03G3/30 , H03K19/096
CPC分类号： H03G1/04 , H03F3/2173 , H03G3/3026 , H03K19/00323 , H03K19/01728 , H03K19/096 , H03K19/20 , H03F2200/78
摘要： In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.

5. 发明授权

US11486928B2 Electronic circuit and corresponding method of testing electronic circuits 有权
公开(公告)号：US11486928B2
公开(公告)日：2022-11-01
申请号：US17159511
申请日：2021-01-27
申请人： STMicroelectronics S.r.l. , STMicroelectronics (Shenzhen) R&D Co. Ltd
发明人： Ignazio Pisello , Yu Yong Wang , Dario Arena , Qi Yu Liu
IPC分类号： G01R31/3185 , G01R31/317 , G06F1/06
摘要： A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.

6. 发明申请

US20140285258A1 SILENT START CLASS-D AMPLIFIER 有权
标题翻译：静音启动类D放大器
公开(公告)号：US20140285258A1
公开(公告)日：2014-09-25
申请号：US14199773
申请日：2014-03-06
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd.
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03F3/217
CPC分类号： H03F3/2171 , H03F3/2175
摘要： A Class-D amplifier includes a pre-amplifier having an input configured to receive an amplifier reference voltage signal which is ramped at start-up at a fast rate. An integrator has a first input configured to receive an input signal from the pre-amplifier and a second input configured to receive an integrator reference voltage signal which is ramped at start-up at a slower rate. A modulator has an input coupled to an output of the integrator. The modulator generates a pulse width modulated output signal. Operation of the Class-D amplifier is controlled at start-up by applying a slow ramped signal as the integrator reference voltage signal and a fast ramped signal as the amplifier reference voltage so that the pulse width modulated output signal exhibits an increasing change in duty cycle in response to an increasing voltage of the integrator reference voltage signal, and no “pop” is introduced at start-up.
摘要翻译： D类放大器包括前置放大器，其具有被配置为接收在启动时以快速速率斜坡的放大器参考电压信号的输入。积分器具有被配置为从前置放大器接收输入信号的第一输入和被配置为接收以较慢速率在启动时斜坡上升的积分器参考电压信号的第二输入。调制器具有耦合到积分器的输出的输入。调制器产生脉宽调制输出信号。通过将缓慢斜坡信号作为积分器参考电压信号和快速斜坡信号作为放大器参考电压来控制D类放大器的工作，使得脉宽调制输出信号在占空比上呈现增加的变化响应于积分器参考电压信号的增加的电压，并且在启动时不引入“弹出”。

7. 发明申请

US20200295723A1 Deglitching Circuit and Method in Class-D Amplifier 审中-公开
公开(公告)号：US20200295723A1
公开(公告)日：2020-09-17
申请号：US16354760
申请日：2019-03-15
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd.
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03G1/04 , H03K19/017 , H03F3/217 , H03K19/096 , H03K19/20 , H03K19/003 , H03G3/30
摘要： In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.

8. 发明授权

US10530309B2 Methods and circuits to reduce pop noise in an audio device 有权
公开(公告)号：US10530309B2
公开(公告)日：2020-01-07
申请号：US16222281
申请日：2018-12-17
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03F1/32 , H03F1/30 , H03F1/02 , H03F3/45 , H03F3/183 , H03F3/185 , H03F3/187 , H03F3/21 , H03F3/217 , H03G3/34 , H04R3/00
摘要： A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

9. 发明授权

US09306523B2 Methods and circuits to reduce pop noise in an audio device 有权
标题翻译：减少音频设备弹奏噪音的方法和电路
公开(公告)号：US09306523B2
公开(公告)日：2016-04-05
申请号：US14478531
申请日：2014-09-05
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd.
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H04R3/00 , H03G3/34
CPC分类号： H03F1/3205 , H03F1/0205 , H03F1/305 , H03F3/183 , H03F3/185 , H03F3/187 , H03F3/211 , H03F3/2171 , H03F3/2173 , H03F3/45179 , H03F2200/03 , H03F2200/351 , H03F2203/21106 , H03F2203/45151 , H03F2203/45156 , H03G3/345 , H03G3/348 , H04R3/002
摘要： A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.
摘要翻译： D类放大器接收和放大差分模拟信号，然后差分模拟信号被差分地积分。两个脉冲宽度调制器产生对应于差分集成模拟信号的脉冲信号，两个功率单元产生输出脉冲信号。功率单元的输出通过电阻反馈网络耦合到积分器的输入端。模拟输出单元将脉冲信号转换为输出模拟信号。差分积分电路实现静音/非静音之间的软转换。静音时，积分器输出是固定的。在软转换期间，PWM输出从固定的50％占空比缓慢变化到最终值，以确保由于模式更改而导致输出中没有弹出式噪声。

10. 发明授权

US09231535B2 Silent start class-D amplifier 有权
标题翻译：静音启动D类放大器
公开(公告)号：US09231535B2
公开(公告)日：2016-01-05
申请号：US14199773
申请日：2014-03-06
申请人： STMicroelectronics (Shenzhen) R&D Co. Ltd.
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03F3/38 , H03F3/217
CPC分类号： H03F3/2171 , H03F3/2175
摘要： A Class-D amplifier includes a pre-amplifier having an input configured to receive an amplifier reference voltage signal which is ramped at start-up at a fast rate. An integrator has a first input configured to receive an input signal from the pre-amplifier and a second input configured to receive an integrator reference voltage signal which is ramped at start-up at a slower rate. A modulator has an input coupled to an output of the integrator. The modulator generates a pulse width modulated output signal. Operation of the Class-D amplifier is controlled at start-up by applying a slow ramped signal as the integrator reference voltage signal and a fast ramped signal as the amplifier reference voltage so that the pulse width modulated output signal exhibits an increasing change in duty cycle in response to an increasing voltage of the integrator reference voltage signal, and no “pop” is introduced at start-up.
摘要翻译： D类放大器包括前置放大器，其具有被配置为接收在启动时以快速速率斜坡的放大器参考电压信号的输入。积分器具有被配置为从前置放大器接收输入信号的第一输入和被配置为接收以较慢速率在启动时斜坡上升的积分器参考电压信号的第二输入。调制器具有耦合到积分器的输出的输入。调制器产生脉宽调制输出信号。通过将缓慢斜坡信号作为积分器参考电压信号和快速斜坡信号作为放大器参考电压来控制D类放大器的工作，使得脉宽调制输出信号在占空比上呈现增加的变化响应于积分器参考电压信号的增加的电压，并且在启动时不引入“弹出”。

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