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1. 发明申请

US20090076751A1 SYSTEMS AND METHODS FOR MEASURING SIGNAL WAVEFORMS 审中-公开
标题翻译：用于测量信号波形的系统和方法
公开(公告)号：US20090076751A1
公开(公告)日：2009-03-19
申请号：US12172257
申请日：2008-07-13
申请人： SHEN-CHUN LI , SHOU-KUO HSU , HSIEN-CHUAN LIANG , HUNG CHAO , DUEN-YI HO , YING-TSO LAI
发明人： SHEN-CHUN LI , SHOU-KUO HSU , HSIEN-CHUAN LIANG , HUNG CHAO , DUEN-YI HO , YING-TSO LAI
IPC分类号： G01R13/00
CPC分类号： G01R13/0272
摘要： A system for measuring a signal waveform is provided. The system comprises a parameter receiving module, a waveform receiving module, a waveform filter, and a data storing module. The parameter receiving module is configured for receiving one or more filtration conditions. The waveform receiving module is configured for receiving the signal waveform. The waveform filter is configured for filtering the signal waveform to obtain a desired waveform. The data storing module is configured for storing the desired waveform into a storage device.
摘要翻译：提供了一种用于测量信号波形的系统。该系统包括参数接收模块，波形接收模块，波形滤波器和数据存储模块。参数接收模块被配置为接收一个或多个过滤条件。波形接收模块被配置为接收信号波形。波形滤波器被配置为对信号波形进行滤波以获得期望的波形。数据存储模块被配置为将期望的波形存储到存储设备中。

2. 发明申请

US20090076778A1 SYSTEM AND METHOD FOR DESIGNING A VOLTAGE REGULATOR MODULE 有权
标题翻译：用于设计电压调节器模块的系统和方法
公开(公告)号：US20090076778A1
公开(公告)日：2009-03-19
申请号：US12172258
申请日：2008-07-13
申请人： SHOU-KUO HSU , YING-TSO LAI , DUEN-YI HO
发明人： SHOU-KUO HSU , YING-TSO LAI , DUEN-YI HO
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer-implemented method for designing a voltage regulator module (VRM) is disclosed. The method includes receiving design parameters and a component data for each component and storing the design parameters and the component data for each component into a component selection table, calculating a work efficiency of the VRM, and storing the work efficiency into a power computation table. The method further includes simulating a derating of each component according to a corresponding rated stress of each component if the work efficiency is greater than or equal to a predetermined work efficiency, calculating a stress ratio of each component, and storing the stress ratio into a component derating table. The component selection table, the power computation table and the component derating table are stored to form a desired VRM model if the stress ratio of each component meets a corresponding derating specification.
摘要翻译：公开了一种用于设计电压调节器模块（VRM）的计算机实现的方法。该方法包括接收每个组件的设计参数和组件数据，并将每个组件的设计参数和组件数据存储到组件选择表中，计算VRM的工作效率，并将工作效率存储在功率计算表中。该方法还包括如果工作效率大于或等于预定工作效率，则计算每个部件的应力比，并将应力比存储到部件中，根据每个部件的相应的额定应力来模拟每个部件的降额降额表。存储组件选择表，功率计算表和组件降额表，以形成所需的VRM模型，如果每个组件的应力比满足相应的降额规范。

3. 发明申请

US20100253383A1 CIRCUIT TOPOLOGY FOR MULTIPLE LOADS 有权
标题翻译：多负载电路拓扑
公开(公告)号：US20100253383A1
公开(公告)日：2010-10-07
申请号：US12425394
申请日：2009-04-17
申请人： HSIAO-YUN SU , YING-TSO LAI , SHOU-KUO HSU
发明人： HSIAO-YUN SU , YING-TSO LAI , SHOU-KUO HSU
IPC分类号： H03K19/003
CPC分类号： H05K1/0246 , H05K2201/044 , H05K2201/09727
摘要： A circuit topology for multiple loads includes a driving terminal for transmitting a driving signal, a number of transmitting lines, and a number of loads operable to receive the driving signal from the driving terminal. The number of loads are connected to the driving terminal one by one via the number of transmitting lines. Two transmitting lines of the number of transmitting lines, which are nearest and farthest respectively from the driving terminal, are both greater than widths of the other transmitting lines.
摘要翻译：用于多个负载的电路拓扑包括用于发送驱动信号的驱动端子，多个发送线路和可操作以从驱动端子接收驱动信号的多个负载。负载数量通过传输线数量逐个连接到驱动端子。距离驱动终端最近和最远的发送线数目的两条发送线都大于其他发送线的宽度。

4. 发明申请

US20100101837A1 PRINTED CIRCUIT BOARD 失效
标题翻译：印刷电路板
公开(公告)号：US20100101837A1
公开(公告)日：2010-04-29
申请号：US12331444
申请日：2008-12-10
申请人： YING-TSO LAI , TSUNG-SHENG HUANG , SHOU-KUO HSU
发明人： YING-TSO LAI , TSUNG-SHENG HUANG , SHOU-KUO HSU
IPC分类号： H05K1/02
CPC分类号： H05K1/0265 , H05K1/114 , H05K1/115 , H05K2201/094 , H05K2201/0979 , H05K2201/09854 , H05K2201/10189
摘要： A printed circuit board includes a reference layer, at least one first hole defined in the reference layer and adjacent from a first pin in a first column of pins of an electronic component, and at least one second hole defined in the reference layer and adjacent from a second pin of the electronic component. The at least one second hole is defined in the reference layer and opposite to the at least one first hole. The second pin is in a neighboring second column of pins from the first column of pins. A diameter of the at least one first hole is greater than a diameter of the at least one second hole such that a difference in current flowing through the first pin and the second pin is reduced.
摘要翻译：印刷电路板包括参考层，限定在参考层中并与电子部件的第一列销中的第一销相邻的至少一个第一孔以及限定在参考层中并与参考层相邻的至少一个第二孔电子部件的第二引脚。至少一个第二孔限定在参考层中并与至少一个第一孔相对。第二引脚位于与第一列引脚相邻的第二列引脚中。所述至少一个第一孔的直径大于所述至少一个第二孔的直径，使得流过所述第一销和所述第二销的电流差减小。

5. 发明申请

US20100050136A1 SYSTEM AND METHOD FOR OPTIMIZING ANALOG CIRCUIT DESIGNS 失效
标题翻译：用于优化模拟电路设计的系统和方法
公开(公告)号：US20100050136A1
公开(公告)日：2010-02-25
申请号：US12257366
申请日：2008-10-23
申请人： YING-TSO LAI , TSUNG-SHENG HUANG , SHOU-KUO HSU
发明人： YING-TSO LAI , TSUNG-SHENG HUANG , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/10
摘要： A system for optimizing analog circuit designs includes an input device, a data processing device, and a data storage device. The data processing device includes a selecting module, a calculation module, and a determining module. The selecting module is for receiving input from the input device and selecting electronic components composing the circuit from the data storage device. The calculation module is for calculating average values and standard deviations of each electronic component, generating normal distribution samples of each electronic component, and calculating output voltages of the circuit. The determining module is for determining whether the circuit meets a process capability standard.
摘要翻译：用于优化模拟电路设计的系统包括输入装置，数据处理装置和数据存储装置。数据处理装置包括选择模块，计算模块和确定模块。选择模块用于从输入设备接收输入，并从数据存储设备中选择构成电路的电子元件。计算模块用于计算每个电子部件的平均值和标准偏差，产生每个电子部件的正态分布样本，以及计算电路的输出电压。确定模块用于确定电路是否满足过程能力标准。

6. 发明申请

US20090294168A1 PRINTED CIRCUIT BOARD 有权
标题翻译：印刷电路板
公开(公告)号：US20090294168A1
公开(公告)日：2009-12-03
申请号：US12272797
申请日：2008-11-18
申请人： YU-CHANG PAI , SHOU-KUO HSU , CHIEN-HUNG LIU , YING-TSO LAI
发明人： YU-CHANG PAI , SHOU-KUO HSU , CHIEN-HUNG LIU , YING-TSO LAI
IPC分类号： H05K1/11
CPC分类号： H05K1/116 , H05K1/0245 , H05K1/0251 , H05K1/165 , H05K3/429 , H05K2201/09236 , H05K2201/09281 , H05K2201/09636
摘要： A printed circuit board includes a first layout layer, a second layout layer, a copper foil layer, a first via and a second via. The first layout layer has a first signal line and a second signal line, each of which has a curved first portion. The second layout layer has a third signal line and a fourth signal line, each of which also has a curved first portion. The curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line are coupled to the first via and the second via. In this case, the curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line cooperatively generate spiral inductance characteristic.
摘要翻译：印刷电路板包括第一布局层，第二布局层，铜箔层，第一通孔和第二通孔。第一布局层具有第一信号线和第二信号线，每条信号线都具有弯曲的第一部分。第二布局层具有第三信号线和第四信号线，每条信号线还具有弯曲的第一部分。第一信号线，第二信号线，第三信号线和第四信号线的弯曲的第一部分耦合到第一通孔和第二通孔。在这种情况下，第一信号线，第二信号线，第三信号线和第四信号线的弯曲的第一部分协同地产生螺旋电感特性。

7. 发明申请

US20090089474A1 MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORY 审中-公开
标题翻译：支持不同类型的内存的主板
公开(公告)号：US20090089474A1
公开(公告)日：2009-04-02
申请号：US11954235
申请日：2007-12-12
申请人： YING-TSO LAI , SHOU-KUO HSU
发明人： YING-TSO LAI , SHOU-KUO HSU
IPC分类号： G06F13/00
CPC分类号： G06F13/4072 , G06F13/4086 , G06F13/4234
摘要： An exemplary motherboard for supporting different types of memory includes a driving module, a first slot, a second slot, and a transmission line connected the driving module, the first slot and the second slot in turn. The first slot is arranged for mounting a first type of memory. The second slot is arranged for mounting a second type of memory. The first memory and the second memory are alternatively mounted on the motherboard. The transmission line is grounded via a capacitor for eliminating echo signals generated by the first and second type memories. The motherboard for supporting different memory modes satisfies different type memories, and maintains integrality of signals transmitted therein.
摘要翻译：用于支持不同类型存储器的示例性母板包括驱动模块，第一槽，第二槽和依次连接驱动模块，第一槽和第二槽的传输线。第一个插槽用于安装第一种类型的存储器。第二槽被安排用于安装第二类型的存储器。第一存储器和第二存储器替代地安装在主板上。传输线通过用于消除由第一和第二类型存储器产生的回波信号的电容器接地。用于支持不同存储模式的主板满足不同类型的存储器，并且保持其中传输的信号的完整性。

8. 发明申请

US20070170971A1 SIGNAL TRANSMITTING CIRCUIT 审中-公开
标题翻译：信号发送电路
公开(公告)号：US20070170971A1
公开(公告)日：2007-07-26
申请号：US11309216
申请日：2006-07-13
申请人： YING-TSO LAI , SHOU-KUO HSU
发明人： YING-TSO LAI , SHOU-KUO HSU
IPC分类号： H03K5/08
CPC分类号： H03K5/15046 , H04L25/0278 , H04L25/08
摘要： A signal transmitting circuit includes a driving circuit, and a plurality of receiving circuits receiving signals transmitted from the driving circuit. Each of the receiving circuits is coupled to the driving circuit consecutively via a transmission line. A filter means is coupled with a segment of the transmission line of two neighboring receiving circuits for filtering signal reflections from the receiving circuits.
摘要翻译：信号发送电路包括驱动电路和接收从驱动电路发送的信号的多个接收电路。每个接收电路经由传输线连续地连接到驱动电路。滤波器装置与两个相邻接收电路的传输线的一段相耦合，用于滤波来自接收电路的信号反射。

9. 发明申请

US20110179660A1 PROBE APPARATUS 失效
标题翻译：探测器
公开(公告)号：US20110179660A1
公开(公告)日：2011-07-28
申请号：US12784511
申请日：2010-05-21
申请人： SHEN-CHUN LI , SHOU-KUO HSU , HSIEN-CHUAN LIANG , YING-TSO LAI
发明人： SHEN-CHUN LI , SHOU-KUO HSU , HSIEN-CHUAN LIANG , YING-TSO LAI
IPC分类号： G01B5/00 , F16H1/18
CPC分类号： G01B3/20 , Y10T74/19698
摘要： An exemplary probe apparatus includes a fixture, a first probe assembly, a motor, a lead screw, two guide members, a second probe, and a reduction gear unit. The first probe assembly is fixedly attached to the fixture and includes a first probe. The motor has a drive shaft attached to the fixture. The lead screw is coupled to the fixture. The two guide members are attached to the fixture and parallel to the lead screw. The second probe assembly is moveably attached to the lead screw and the at least one guide member, and includes a second probe. The reduction gear unit is coupled to the drive shaft and the lead screw to transmit power from the motor to the second probe assembly through the lead screw. The second probe assembly is configured for moving the second probe towards or away from the first probe along the two guide members.
摘要翻译：示例性探针装置包括固定装置，第一探针组件，马达，导螺杆，两个引导构件，第二探针和减速装置。第一探针组件固定地附接到固定装置并且包括第一探针。电动机具有连接到固定装置的驱动轴。导螺杆联接到固定装置。两个引导构件连接到夹具并平行于导螺杆。第二探针组件可移动地附接到导螺杆和至少一个引导构件，并且包括第二探针。减速齿轮单元联接到驱动轴和导螺杆，以将动力从马达通过丝杠传递到第二探针组件。第二探针组件被构造成沿着两个引导构件将第二探针朝向或远离第一探头移动。

10. 发明申请

US20110038427A1 DIFFERENTIAL SIGNAL TRANSMISSION DEVICE 失效
标题翻译：差分信号传输装置
公开(公告)号：US20110038427A1
公开(公告)日：2011-02-17
申请号：US12560445
申请日：2009-09-16
申请人： SHOU-KUO HSU , CHENG-HSIEN LEE , YING-TSO LAI , HSIAO-YUN SU , JIA-CHI CHEN
发明人： SHOU-KUO HSU , CHENG-HSIEN LEE , YING-TSO LAI , HSIAO-YUN SU , JIA-CHI CHEN
IPC分类号： H04L27/00
CPC分类号： H04L25/0272
摘要： A differential signal transmission device transmits N differential signal pairs from a differential signal generator to a number of receiving terminals. The N differential signal pairs include N positive signals and N negative signals. The N positive signals are clustered at a first positive clustering point. The first positive clustering point is connected to a second positive clustering point via a first matching resistor. The second positive clustering point is grounded via a first grounding resistor, and outputs a number of positive signals to the number of receiving terminals respectively. The N negative signals are clustered at a first negative clustering point. The first negative clustering point is connected to a second negative clustering point via a second matching resistor. The second negative signal clustering point is grounded via a second grounding resistor, and outputs a number of negative signals to the number of receiving terminals respectively.
摘要翻译：差分信号传输装置将差分信号发生器的N个差分信号对发送到多个接收终端。 N个差分信号对包括N个正信号和N个负信号。 N个正信号聚集在第一个正聚类点。第一正聚集点通过第一匹配电阻连接到第二正聚集点。第二个正聚集点通过第一接地电阻接地，并分别输出多个正信号到接收端的数量。 N个负信号聚集在第一个负聚类点。第一负聚集点通过第二匹配电阻器连接到第二负聚集点。第二负信号聚簇点通过第二接地电阻接地，并分别输出多个负信号至接收端数。

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