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1. 发明申请

US20190181145A1 METHOD AND DEVICE TO REDUCE FINFET SRAM CONTACT RESISTANCE 审中-公开
公开(公告)号：US20190181145A1
公开(公告)日：2019-06-13
申请号：US15967471
申请日：2018-04-30
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
发明人： NAN WANG
IPC分类号： H01L27/11 , H01L27/088 , H01L29/66 , G11C11/412
CPC分类号： H01L27/11 , G11C11/412 , H01L27/0886 , H01L29/6681
摘要： A static random access memory includes a substrate, fins on the substrate and including a first fin for a first pull-up transistor, a second fin for a second pull-up transistor, a third fin for a first pass-gate transistor and a first pull-down transistor, and a fourth fin for a second pass-gate transistor and a second pull-down transistor, dummy fins on the substrate, gate structures on the fins for forming transistors, first and second recesses in the fins on opposite sides of the gate structures, third recesses in the dummy fins, a first epitaxial region in the first recess, a second epitaxial region in the second recess, a third epitaxial region in the third recess, a merged epitaxial region including the third epitaxial region and the first epitaxial region or the third epitaxial region and the second epitaxial region, and a contact member on the merged epitaxial region.

2. 发明申请

US20160155492A1 NOVEL FINFET 6T SRAM CELL STRUCTURE 有权
标题翻译：新款FINFET 6T SRAM单元结构
公开(公告)号：US20160155492A1
公开(公告)日：2016-06-02
申请号：US14921963
申请日：2015-10-23
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
发明人： GONG ZHANG , NAN WANG
IPC分类号： G11C11/419 , H01L27/11
CPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A static memory circuit includes a pull-up transistor, a pull-down transistor, a pass-gate transistor associated with the pull-up and pull-down transistors, and first and second word lines electrically insulated from each other. The pass-gate transistor includes a number of Fins and a gate electrode having a number of first and second gates, each one of the gates is disposed on one of the Fins, the first gates are connected to the first word line, and the second gates are connected to the second word line. During a read operation, one of the first and second word lines is asserted low, so that the beta ratio is greater than or equal to a first predetermined value. During a write operation, one of the first and second word lines is asserted high; so that a gamma ratio is greater than or equal to a second predetermined value.
摘要翻译：静态存储器电路包括上拉晶体管，下拉晶体管，与上拉和下拉晶体管相关联的通过栅极晶体管，以及彼此电绝缘的第一和第二字线。栅极晶体管包括多个Fins和具有多个第一和第二栅极的栅电极，每个栅极设置在Fins中的一个上，第一栅极连接到第一字线，第二栅极连接到第一栅极门连接到第二字线。在读取操作期间，第一和第二字线中的一个被断言为低，使得β比率大于或等于第一预定值。在写入操作期间，第一和第二字线之一被断言为高; 使得伽马比例大于或等于第二预定值。

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