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1. 发明授权

US09886342B2 Storage device operations based on bit error rate (BER) estimate 有权
公开(公告)号：US09886342B2
公开(公告)日：2018-02-06
申请号：US14925676
申请日：2015-10-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yuri Ryabinin , Eran Banani , Yan Dumchin , Mark Naumenko , Alexander Mostovoy , Mark Fiterman
IPC分类号： H03M13/00 , G06F11/10 , G11C29/52 , H03M13/11 , G06F3/06 , H03M13/37
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1012 , G11C29/52 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/612 , H03M13/6325
摘要： A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.

2. 发明申请

US20170123898A1 STORAGE DEVICE OPERATIONS BASED ON BIT ERROR RATE (BER) ESTIMATE 有权
公开(公告)号：US20170123898A1
公开(公告)日：2017-05-04
申请号：US14925676
申请日：2015-10-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yuri Ryabinin , Eran Banani , Yan Dumchin , Mark Naumenko , Alexander Mostovoy , Mark Fiterman
IPC分类号： G06F11/10 , H03M13/11 , G06F3/06 , G11C29/52
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1012 , G11C29/52 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/612 , H03M13/6325
摘要： A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.

3. 发明申请

US20150254384A1 Virtual Critical Path (VCP) System and Associated Methods 有权
标题翻译：虚拟关键路径（VCP）系统及相关方法
公开(公告)号：US20150254384A1
公开(公告)日：2015-09-10
申请号：US14198374
申请日：2014-03-05
申请人： SanDisk Technologies Inc.
发明人： Yan Dumchin , Yair Baram , Michael Tomashev , Leonid Minz , Yevgeny Kaplan , Suzanna Zilberman
IPC分类号： G06F17/50
CPC分类号： H03L7/07 , G01R31/28 , G01R31/31725 , G06F1/08 , G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.
摘要翻译：虚拟关键路径（VCP）电路与实际关键路径电路分开定义。 VCP根据特殊的时钟信号进行工作。实际的关键路径电路根据系统时钟信号进行工作。 VCP电路具有与实际的关键路径电路基本相等的信号定时特性。 VCP电路包括被定义为基于输入值计算输出值的计算电路和被定义为将输出值与预期结果值进行比较的比较电路。由VCP电路计算的输出值与预期结果值之间的匹配表示特殊时钟信号的频率是可接受的。 VCP电路用于确定特殊时钟信号的最大可接受频率。然后将系统时钟信号的频率设置为特殊时钟信号的最大可接受频率。

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