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1. 发明授权

US09047973B2 Group word line erase and erase-verify methods for 3D non-volatile memory 有权
标题翻译：用于3D非易失性存储器的组字线擦除和擦除验证方法
公开(公告)号：US09047973B2
公开(公告)日：2015-06-02
申请号：US14273900
申请日：2014-05-09
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Alex Mak , Johann Alsmeier , Man L Mui
IPC分类号： G11C11/34 , G11C16/34 , G11C16/14
CPC分类号： G11C16/3445 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/344 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
摘要翻译：根据预期的擦除速度将存储元件分配给组的3D堆叠存储器件的擦除操作。然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。可以将所有组一起设置为擦除或禁止状态。在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

2. 发明申请

US20150063033A1 Selective Word Line Erase In 3D Non-Volatile Memory 有权
标题翻译： 3D非易失性存储器中的选择性字线擦除
公开(公告)号：US20150063033A1
公开(公告)日：2015-03-05
申请号：US14536923
申请日：2014-11-10
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , H01L27/11582 , H01L29/7926
摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.
摘要翻译：用于3D堆叠存储器件的擦除处理允许擦除存储单元块的一部分。在一种方法中，在U形NAND串配置中，漏极或源极侧列中的存储单元被擦除。在另一种方法中，例如在U形或直的NAND串配置中，擦除存储器单元列的一部分中的存储单元，并且在擦除和未擦除的存储器单元之间提供虚拟存储单元。虚拟存储器单元可以在擦除存储器单元的任一侧（例如，高于和低于），或者在未擦除的存储器单元的任一侧上。虚拟存储单元不能存储用户数据，但是由于电容耦合，防止擦除的存储单元的阈值电压的降档改变未擦除的存储单元的阈值电压。

3. 发明授权

US09361986B2 High endurance non-volatile storage 有权
标题翻译：高耐久性非易失性存储
公开(公告)号：US09361986B2
公开(公告)日：2016-06-07
申请号：US13622045
申请日：2012-09-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
IPC分类号： G11C16/10 , G11C5/06 , G11C11/56
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

4. 发明授权

US09105349B2 Adaptive operation of three dimensional memory 有权
标题翻译：三维记忆的自适应操作
公开(公告)号：US09105349B2
公开(公告)日：2015-08-11
申请号：US14281404
申请日：2014-05-19
申请人： SanDisk Technologies Inc.
发明人： Chris Avila , Gautam Dusija , Jian Chen , Yingda Dong , Man Mui , Seungpil Lee , Alex Mak
IPC分类号： G11C11/34 , G11C16/34 , G11C29/04 , G06F11/10 , G06F11/14
CPC分类号： G11C16/3404 , G06F11/1048 , G06F11/141 , G06F11/1497 , G11C29/04
摘要： When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.
摘要翻译：当通过误差校正码（ECC）将来自三维NAND存储器阵列的一部分的数据确定为不可校正时，确定在大于该部分的整个单元中ECC是否不可纠正数据。如果修改的读取条件提供ECC可校正数据，则修改的读取条件被记录以用于较大单元的后续读取。

5. 发明授权

US09330778B2 Group word line erase and erase-verify methods for 3D non-volatile memory 有权
标题翻译：用于3D非易失性存储器的组字线擦除和擦除验证方法
公开(公告)号：US09330778B2
公开(公告)日：2016-05-03
申请号：US14524153
申请日：2014-10-27
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Alex Mak , Johann Alsmeier , Man L Mui
IPC分类号： G11C16/10 , G11C16/34 , G11C16/14 , G11C11/56 , G11C16/04 , H01L27/115
CPC分类号： G11C16/3445 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/344 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
摘要翻译： 3D堆叠存储器件的擦除操作根据预期的擦除速度将存储元件分配给组。然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。可以将所有组一起设置为擦除或禁止状态。在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

6. 发明授权

US09092363B2 Selection of data for redundancy calculation in three dimensional nonvolatile memory 有权
标题翻译：在三维非易失性存储器中选择用于冗余计算的数据
公开(公告)号：US09092363B2
公开(公告)日：2015-07-28
申请号：US14281243
申请日：2014-05-19
申请人： SanDisk Technologies Inc.
发明人： Chris Avila , Gautam Dusija , Jian Chen , Yingda Dong , Man Mui , Seungpil Lee , Alex Mak
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04 , G06F12/02 , G11C16/34
CPC分类号： G06F11/1068 , G06F12/0246 , G11C16/0483 , G11C16/349 , G11C29/04 , G11C29/82 , G11C2213/71
摘要： Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block.
摘要翻译：基于它们用于计算冗余数据的位置来选择存储在三维存储器阵列中的部分数据。选择位置，使得给定计算的一组部分中的两个部分可能在同一时间变得不可校正。所选择的部分可以被至少一个字线分隔开并且被块中的至少一个字符串隔开。

7. 发明申请

US20140355345A1 Adaptive Operation of Three Dimensional Memory 有权
公开(公告)号：US20140355345A1
公开(公告)日：2014-12-04
申请号：US14281404
申请日：2014-05-19
申请人： SanDisk Technologies Inc.
发明人： Chris Avila , Gautam Dusija , Jian Chen , Yingda Dong , Man Mui , Seungpil Lee , Alex Mak
IPC分类号： G11C16/34 , G11C29/04
CPC分类号： G11C16/3404 , G06F11/1048 , G06F11/141 , G06F11/1497 , G11C29/04
摘要： When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.

8. 发明申请

US20140247668A1 Group Word Line Erase And Erase-Verify Methods For 3D Non-Volatile Memory 有权
标题翻译：用于3D非易失性存储器的组字行擦除和擦除验证方法
公开(公告)号：US20140247668A1
公开(公告)日：2014-09-04
申请号：US14273900
申请日：2014-05-09
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Alex Mak , Johann Alsmeier , Man L. Mui
IPC分类号： G11C16/34 , G11C16/14
CPC分类号： G11C16/3445 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/344 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
摘要翻译：根据预期的擦除速度将存储元件分配给组的3D堆叠存储器件的擦除操作。然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。可以将所有组一起设置为擦除或禁止状态。在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

9. 发明申请

US20140226414A1 GROUP WORD LINE ERASE AND ERASE-VERIFY METHODS FOR 3D NON-VOLATILE MEMORY 有权
标题翻译：用于3D非易失性存储器的组字线删除和删除验证方法
公开(公告)号：US20140226414A1
公开(公告)日：2014-08-14
申请号：US13767708
申请日：2013-02-14
申请人： SANDISK TECHNOLOGIES INC.
发明人： Xiying Costa , Alex Mak , Johann Alsmeier , Man L. Mui
IPC分类号： G11C16/14
CPC分类号： G11C16/3445 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/344 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
摘要翻译：根据预期的擦除速度将存储元件分配给组的3D堆叠存储器件的擦除操作。然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。可以将所有组一起设置为擦除或禁止状态。在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

10. 发明授权

US09318206B2 Selective word line erase in 3D non-volatile memory 有权
标题翻译： 3D非易失性存储器中的选择性字线擦除
公开(公告)号：US09318206B2
公开(公告)日：2016-04-19
申请号：US14536923
申请日：2014-11-10
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
IPC分类号： G11C16/14 , G11C16/04 , G11C16/16 , H01L29/792 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , H01L27/11582 , H01L29/7926
摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.
摘要翻译：用于3D堆叠存储器件的擦除处理允许擦除存储单元块的一部分。在一种方法中，在U形NAND串配置中，漏极或源极侧列中的存储单元被擦除。在另一种方法中，例如在U形或直的NAND串配置中，擦除存储器单元列的一部分中的存储单元，并且在擦除和未擦除的存储器单元之间提供虚拟存储单元。虚拟存储器单元可以在擦除存储器单元的任一侧（例如，高于和低于），或者在未擦除的存储器单元的任一侧上。虚拟存储单元不能存储用户数据，但是由于电容耦合，防止擦除的存储单元的阈值电压的降档改变未擦除的存储单元的阈值电压。

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