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1. 发明授权

US09646981B2 Passive devices for integration with three-dimensional memory devices 有权
公开(公告)号：US09646981B2
公开(公告)日：2017-05-09
申请号：US14739284
申请日：2015-06-15
申请人： SanDisk Technologies, Inc.
发明人： Masatoshi Nishikawa , Ryoichi Honma , Toru Miwa , Masahide Matsumoto , Yuki Mizutani , Hiroaki Koketsu
IPC分类号： G11C16/08 , G11C5/02 , G11C5/06 , G11C5/14 , G11C7/06 , H01L27/11526 , H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L49/02 , G11C16/04
CPC分类号： H01L27/11526 , G11C5/02 , G11C5/025 , G11C5/06 , G11C5/063 , G11C5/14 , G11C16/0483 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L28/20 , H01L28/40
摘要： A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.

2. 发明授权

US09142298B2 Efficient smart verify method for programming 3D non-volatile memory 有权
公开(公告)号：US09142298B2
公开(公告)日：2015-09-22
申请号：US13940504
申请日：2013-07-12
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Cynthia Hsu , Man L Mui , Manabu Sakai , Toru Miwa , Masaaki Higashitani
IPC分类号： G11C16/00 , G11C16/10 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3468 , G11C16/349
摘要： In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.

3. 发明授权

US09691781B1 Vertical resistor in 3D memory device with two-tier stack 有权
公开(公告)号：US09691781B1
公开(公告)日：2017-06-27
申请号：US14959169
申请日：2015-12-04
申请人： SanDisk Technologies Inc.
发明人： Masatoshi Nishikawa , Kota Funayama , Toru Miwa , Hiroyuki Ogawa
IPC分类号： H01L27/11573 , H01L27/1157 , H01L27/11578 , H01L49/02 , H01L21/283 , H01L21/225
CPC分类号： H01L27/11582 , H01L21/2253 , H01L21/283 , H01L21/76883 , H01L21/76897 , H01L23/5226 , H01L23/5228 , H01L27/11524 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L28/20
摘要： A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

4. 发明申请

US20170162592A1 VERTICAL RESISTOR IN 3D MEMORY DEVICE WITH TWO-TIER STACK 有权
公开(公告)号：US20170162592A1
公开(公告)日：2017-06-08
申请号：US14959169
申请日：2015-12-04
申请人： SanDisk Technologies Inc.
发明人： Masatoshi Nishikawa , Kota Funayama , Toru Miwa , Hiroyuki Ogawa
IPC分类号： H01L27/115 , H01L21/283 , H01L21/225 , H01L49/02
CPC分类号： H01L27/11582 , H01L21/2253 , H01L21/283 , H01L21/76883 , H01L21/76897 , H01L23/5226 , H01L23/5228 , H01L27/11524 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L28/20
摘要： A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

5. 发明授权

US09589981B2 Passive devices for integration with three-dimensional memory devices 有权
标题翻译：用于与三维存储器件集成的无源器件
公开(公告)号：US09589981B2
公开(公告)日：2017-03-07
申请号：US14739354
申请日：2015-06-15
申请人： SanDisk Technologies, Inc.
发明人： Masatoshi Nishikawa , Ryoichi Honma , Toru Miwa , Hiroaki Koketsu , Johann Alsmeier
IPC分类号： H01L27/115 , H01L23/522 , H01L23/528 , H01L49/02 , H01L21/265 , H01L21/768 , H01L21/3205
CPC分类号： H01L27/11582 , H01L21/26513 , H01L21/32055 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L27/0688 , H01L27/11531 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L28/20
摘要： A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.
摘要翻译：三维存储器件包括存储器件区域，该存储器件区域包含多个非易失性存储器件，包含有源驱动器电路器件的外围器件区域以及外围器件区域和存储器器件区域之间的阶梯表面区域，该区域包含多个被动驱动电路设备。

6. 再颁专利

USRE46264E1 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：USRE46264E1
公开(公告)日：2017-01-03
申请号：US14290905
申请日：2014-05-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06 , G11C16/34
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

7. 再颁专利

USRE46014E1 Defective word line detection 有权
标题翻译：字线检测不良
公开(公告)号：USRE46014E1
公开(公告)日：2016-05-24
申请号：US14285459
申请日：2014-05-22
申请人： SANDISK TECHNOLOGIES, INC.
发明人： Manabu Sakai , Toru Miwa
IPC分类号： G11C16/04 , G11C29/02 , G11C11/56 , G11C29/12
CPC分类号： G11C29/025 , G11C11/5628 , G11C16/0483 , G11C2029/1202 , G11C2211/5621
摘要： Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.
摘要翻译：提供了用于检测字线中的缺陷的方法和非易失性存储系统。可能检测到“破碎”的字线缺陷。可以保持关于哪些存储元件被编程为跟踪状态的信息。然后，在完成编程之后，读取存储元件以确定哪些存储元件具有低于与跟踪状态相关联的参考电压电平的阈值电压。通过跟踪哪些存储元件处于跟踪状态，可以滤除与其他状态相关联的元件，使得可以对哪些存储元件被编程不正确进行准确的评估。根据该信息，可以确定字线是否有缺陷。例如，如果存储元素太多被编程不当，则这可能表示一个破损的字线。

8. 发明申请

US20140247662A1 Efficient Smart Verify Method For Programming 3D Non-Volatile Memory 有权
公开(公告)号：US20140247662A1
公开(公告)日：2014-09-04
申请号：US14278374
申请日：2014-05-15
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Cynthia Hsu , Man L. Mui , Manabu Sakai , Toru Miwa , Masaaki Higashitani
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3468 , G11C16/349
摘要： In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.

9. 发明授权

US09595535B1 Integration of word line switches with word line contact via structures 有权
标题翻译：通过结构将字线开关与字线接触集成
公开(公告)号：US09595535B1
公开(公告)日：2017-03-14
申请号：US15046780
申请日：2016-02-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： Hiroyuki Ogawa , Makoto Yoshida , Kazutaka Yoshizawa , Takuya Ariki , Toru Miwa
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/11582 , G11C8/08 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.
摘要翻译：用于三维存储器件的字线解码器电路中的字线切换可以被形成为覆盖接触通孔结构的直线场效应晶体管至用于字线的导电层。覆盖在导电层的阶梯表面上的电介质材料部分中的通孔可以用导电材料填充并凹入以形成接触通孔结构。在凹部中形成下部有源区后，可以形成栅极并图案化以在覆盖接触通孔结构的区域中形成开口。可以在开口的侧壁上形成栅极电介质，并且可以在栅电极的开口内部形成晶体管沟道。上部有源区可以形成在晶体管通道上。

10. 发明授权

US09142302B2 Efficient smart verify method for programming 3D non-volatile memory 有权
标题翻译：高效的智能验证方法用于编程3D非易失性存储器
公开(公告)号：US09142302B2
公开(公告)日：2015-09-22
申请号：US14278374
申请日：2014-05-15
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Cynthia Hsu , Man L Mui , Manabu Sakai , Toru Miwa , Masaaki Higashitani
IPC分类号： G11C16/00 , G11C16/10 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3468 , G11C16/349
摘要： In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.
摘要翻译：在3D堆叠非易失性存储器件的编程操作中，首先将所选字线层上的初始存储器单元集合（其涉及少于所选字线层上的所有存储器单元）作为测试用例来确定最佳值用于编程所选字线层上的剩余存储单元的条件。例如，确定了将初始存储器单元组编程为初始量所需的多个程序验证迭代或循环。然后，该循环计数例如在存储单元的初始组内，剩余存储单元内，剩余字线层或数据寄存器中的存储器单元内存储，并且初始存储单元集合的编程继续完成随后，检索循环计数并用于确定用于编程剩余存储单元的最佳启动程序电压。

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