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1. 发明授权

US10937471B2 Non-volatile memory device and storage device including the same 有权
公开(公告)号：US10937471B2
公开(公告)日：2021-03-02
申请号：US16933768
申请日：2020-07-20
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dong-Su Jang , Man-Jae Yang , Jeong-Don Ihm , Go-Eun Jung , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： G11C7/00 , G11C7/10 , G11C11/4096 , G11C7/22 , G11C11/4076 , G11C5/06 , G11C16/26
摘要： A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

2. 发明授权

US10741225B2 Non-volatile memory device and storage device including the same 有权
公开(公告)号：US10741225B2
公开(公告)日：2020-08-11
申请号：US16802084
申请日：2020-02-26
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dong-Su Jang , Man-Jae Yang , Jeong-Don Ihm , Go-Eun Jung , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： G11C7/00 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C16/26 , G11C5/06
摘要： A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

3. 发明授权

US10340022B2 Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory 有权
公开(公告)号：US10340022B2
公开(公告)日：2019-07-02
申请号：US15977553
申请日：2018-05-11
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： H03K19/177 , G11C29/02 , G11C7/10 , G11C5/06 , G11C16/06 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

4. 发明授权

US10672436B2 Memory device including on-die-termination circuit 审中-公开
公开(公告)号：US10672436B2
公开(公告)日：2020-06-02
申请号：US16058709
申请日：2018-08-08
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： G11C7/10
摘要： A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

5. 发明申请

US20200091021A1 DEFECT DETECTION STRUCTURE OF A SEMICONDUCTOR DIE, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND METHOD OF DETECTING DEFECTS IN SEMICONDUCTOR DIE 审中-公开
公开(公告)号：US20200091021A1
公开(公告)日：2020-03-19
申请号：US16357674
申请日：2019-03-19
申请人： Samsung Electronics Co., Ltd.
发明人： Min-Jae Lee , Sang-Lok Kim , Byung-Hoon Jeong , Tae-Sung Lee , Jeong-Don Ihm , Jae-Yong Jeong , Young-Don Choi
IPC分类号： H01L21/66 , H01L23/528
摘要： A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

6. 发明授权

US10559373B2 Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory 有权
公开(公告)号：US10559373B2
公开(公告)日：2020-02-11
申请号：US16458933
申请日：2019-07-01
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： G11C7/10 , G11C29/02 , G11C5/06 , G11C16/26 , G11C16/10 , G11C16/06
摘要： A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

7. 发明授权

US10291275B2 Reception interface circuits supporting multiple communication standards and memory systems including the same 有权
公开(公告)号：US10291275B2
公开(公告)日：2019-05-14
申请号：US15397012
申请日：2017-01-03
申请人： Samsung Electronics Co., Ltd.
发明人： Seon-Kyoo Lee , Byung-Hoon Jeong , Jeong-Don Ihm , Young-Don Choi
IPC分类号： H03F1/32 , H03F1/34 , H04B1/24 , H04L25/03 , H04L12/863 , H04L25/02 , H04L12/861
摘要： A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

8. 发明授权

US08988929B2 Nonvolatile memory device and related operating method 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US08988929B2
公开(公告)日：2015-03-24
申请号：US14093076
申请日：2013-11-29
申请人： Samsung Electronics Co., Ltd.
发明人： Hyun-Kook Park , Young-Don Choi
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2013/0052 , G11C2213/71 , G11C2213/72
摘要： A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground. The method further includes adjusting at least one of a clamping voltage of the clamping circuit and a resistance of the line resistor according to a relative location of the selected one of the resistance memory cells within the memory cell array, and applying a read current to the sense node and sensing a voltage of the sense node to read a data stored in the selected one of the resistance memory cells.
摘要翻译：一种用于驱动非易失性存储器件的方法，其中非易失性存储器件包括由电阻存储器单元组成的存储单元阵列。该方法包括将感测节点和接地之间的串联的钳位电路，线路电阻器和所选择的电阻存储器单元电连接。该方法还包括根据存储单元阵列内所选择的一个电阻存储器单元的相对位置来调整钳位电路的钳位电压和线路电阻器的电阻中的至少一个，并将读取电流施加到感测节点并且感测感测节点的电压以读取存储在所选择的一个电阻存储器单元中的数据。

9. 再颁专利

USRE49206E1 Nonvolatile memory device, memory system including the same and method of operating the same 有权
公开(公告)号：USRE49206E1
公开(公告)日：2022-09-06
申请号：US16692483
申请日：2019-11-22
申请人： Samsung Electronics Co., Ltd.
发明人： Dae-Woon Kang , Jeong-don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： H03K19/0175 , G11C7/00 , H03H7/38 , G11C5/02 , G11C5/04 , G11C7/10 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/02 , H03K19/00 , G11C16/04 , G11C29/50
摘要： A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

10. 发明授权

US09058874B2 Sensing circuits and phase change memory devices including the same 有权
标题翻译：感测电路和包括相同的相变存储器件
公开(公告)号：US09058874B2
公开(公告)日：2015-06-16
申请号：US13781997
申请日：2013-03-01
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Don Choi , Mu-Hui Park , Hyun-Kook Park , Ickhyun Song
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0009 , G11C13/0069 , G11C2213/72
摘要： A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.
摘要翻译：感测电路包括多个单元读取电流发生器，参考电流发生器和多个读出放大器。每个单元读取电流发生器从多个存储器单元中的每一个生成单元读取电流。参考电流发生器将单元读取电流相加以产生和电流。每个读出放大器基于每个单元读取电流和平均电流来确定存储在每个存储器单元中的数据状态。平均电流是根据和电流获得的。

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