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1. 发明申请

US20150102282A1 SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONAL CROSS POINT ARRAY 有权
标题翻译：具有三维交叉点阵列的半导体存储器件
公开(公告)号：US20150102282A1
公开(公告)日：2015-04-16
申请号：US14506005
申请日：2014-10-03
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： LIJIE ZHANG , YOUNG-BAE KIM , YOUN-SEON KANG , IN-GYU BAEK , MASAYUKI TERAI
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , H01L27/2454 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.
摘要翻译：半导体存储器件包括在垂直于衬底的方向上在衬底上直立延伸的柱，设置在衬底上并由第一层间绝缘层，第一导电层，第二层间绝缘层和第二导电层插入在所述柱和所述第一导电层之间的可变电阻层以及插在所述第一柱和所述第二导电层之间的绝缘层。

2. 发明申请

US20160148977A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20160148977A1
公开(公告)日：2016-05-26
申请号：US14980247
申请日：2015-12-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： JIN-WOO LEE , YOUN-SEON KANG , JUNG-MOO LEE , SEUNG-JAE JUNG , HYUN-SU JU
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1675
摘要： A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

3. 发明申请

US20150129824A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150129824A1
公开(公告)日：2015-05-14
申请号：US14323301
申请日：2014-07-03
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： JIN-WOO LEE , YOUN-SEON KANG , JUNG-MOO LEE , SEUNG-JAE JUNG , HYUN-SU JU
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1675
摘要： A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.
摘要翻译：半导体器件包括衬底上的第一电极，选择器件图案，可变电阻层图案，第一保护层图案，第二保护层图案和第二电极。选择装置图案在给定方向上比可变电阻层图案更宽。第一保护层图案形成在可变电阻层图案的第一对相对侧上。第二保护层图案形成在可变电阻层图案的第二对相对的第二保护层图案上。第二电极设置在可变电阻层图案上。

4. 发明申请

US20170250225A1 VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20170250225A1
公开(公告)日：2017-08-31
申请号：US15595307
申请日：2017-05-15
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： SEUNG-JAE JUNG , YOUN-SEON KANG
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L45/147 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/16
摘要： A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other. Each of the second memory cells includes a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on second plane.

5. 发明申请

US20150340610A1 VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US20150340610A1
公开(公告)日：2015-11-26
申请号：US14607121
申请日：2015-01-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： SEUNG-JAE JUNG , YOUN-SEON KANG
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1293 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/1675
摘要： A variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines over the first conductive lines, which extend in a second direction not parallel to the first direction, memory cells including a variable resistance element, each of which is formed at an intersection of the first and second conductive lines, first insulation layer patterns extending in the first direction between the memory cells, second insulation layer patterns extending in the second direction between the memory cells, first thermal barrier layer patterns extending in the first direction, which is spaced apart from the memory cells in the second direction between the first insulation layer patterns, and second thermal barrier layer patterns extending in the second direction, which is spaced apart from the memory cells in the first direction between the second insulation layer patterns.
摘要翻译：可变电阻存储器件包括沿第一方向延伸的第一导线，在第一导线上方的第二导线，其沿与第一方向不平行的第二方向延伸，存储单元包括可变电阻元件，在第一和第二导线的交叉点处，在存储单元之间沿第一方向延伸的第一绝缘层图案，在存储单元之间沿第二方向延伸的第二绝缘层图案，沿第一方向延伸的第一热障层图案，其在第一绝缘层图案之间的第二方向上与存储单元间隔开，并且在第二绝缘层图案之间沿第一方向与存储单元间隔开的第二方向延伸的第二热障层图案。

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