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1. 发明公开

US20240121952A1 VERTICAL MEMORY DEVICE 审中-公开
公开(公告)号：US20240121952A1
公开(公告)日：2024-04-11
申请号：US18232568
申请日：2023-08-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sohyeon LEE , Seahoon LEE , Jaeduk LEE , Tackhwi LEE
IPC分类号： H10B41/27 , H10B41/10 , H10B43/10 , H10B43/27
CPC分类号： H10B41/27 , H10B41/10 , H10B43/10 , H10B43/27
摘要： A vertical memory device includes a substrate, first and second sub-semiconductor patterns, first and second common source contacts, and first and second cell structures. The substrate includes a first region and a second region having a same length as the first region in a first direction, the first region having a first width in a second direction perpendicular to the first direction, and the second region having a second width in the second direction that is less than the first width. The first sub-semiconductor pattern covers the first region, and a portion of the first sub-semiconductor pattern has a first thickness. The second sub-semiconductor pattern covers the second region and has a second thickness that is less than the first thickness. The first and second common source contacts are disposed on edges in the second direction of the first and second patterns, respectively.

2. 发明公开

US20230307062A1 NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, CONTROLLER FOR CONTROLLING THE SAME, AND STORAGE DEVICE INCLUDING THE SAME 审中-公开
公开(公告)号：US20230307062A1
公开(公告)日：2023-09-28
申请号：US18326606
申请日：2023-05-31
申请人： Samsung Electronics Co., Ltd.
发明人： Soyeong GWAK , Raeyoung LEE , Jinkyu KANG , Sejun PARK , Changhwan SHIN , Jaeduk LEE , Woojae JANG
IPC分类号： G11C16/16 , G11C16/26 , G11C16/34 , G11C7/10 , G11C16/24 , G11C16/08
CPC分类号： G11C16/16 , G11C16/26 , G11C16/349 , G11C7/1087 , G11C16/24 , G11C7/106 , G11C16/08
摘要： An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.

3. 发明公开

US20240282377A1 NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE 审中-公开
公开(公告)号：US20240282377A1
公开(公告)日：2024-08-22
申请号：US18441331
申请日：2024-02-14
申请人： Samsung Electronics Co., Ltd.
发明人： Chaehyeon LIM , Woojae JANG , Sejun PARK , Yujeong SEO , Jaeduk LEE
IPC分类号： G11C16/08 , G11C16/04 , G11C16/32
CPC分类号： G11C16/08 , G11C16/0433 , G11C16/32
摘要： Provided is an operating method of a nonvolatile memory device including a plurality of cell strings, each cell string of the plurality of cell strings including a plurality of memory cells, connected between a bit line and a common source line, and vertical holes penetrating a plurality of word lines stacked in a direction perpendicular to a substrate, the operating method including applying a word line voltage to the plurality of word lines, classifying the plurality of word lines into a plurality of regions, each region of the plurality of regions including at least one of the word lines, and recovering voltages of the plurality of word lines by recovering voltages of word lines arranged in a central region among the plurality of regions before recovering voltages of word lines in other regions of the plurality of regions.

4. 发明申请

US20230042249A1 MEMORY DEVICE STORING SETTING DATA AND OPERATING METHOD THEREOF 有权
公开(公告)号：US20230042249A1
公开(公告)日：2023-02-09
申请号：US17722850
申请日：2022-04-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Guyeon HAN , Sangwon PARK , Jinkyu KANG , Raeyoung LEE , Jaeduk LEE
IPC分类号： G06F3/06
摘要： Provided are a memory device storing setting data and a memory system including the same. The memory device may include a cell array including a plurality of cell blocks, each including a plurality of pages, and a control logic that controls a program and read operation on the cell array, wherein at least one page of the cell array stores information data read (IDR) data including information related to a setting operation of the memory device, at least one other page of the cell array stores replica IDR data including inverted bit values of the IDR data, and the control logic controls a recovery operation for repairing errors in the IDR data by reading the replica IDR data when a read fail of the IDR data occurs.

5. 发明申请

US20230019217A1 NON-VOLATILE MEMORY DEVICE INCLUDING PASS TRANSISTOR 有权
公开(公告)号：US20230019217A1
公开(公告)日：2023-01-19
申请号：US17709790
申请日：2022-03-31
申请人： Samsung Electronics Co., Ltd.
发明人： Tackhwi LEE , Jaeduk LEE , Hojun LEE , Seongpil CHANG
IPC分类号： H01L27/112 , G11C16/08 , G11C16/12
摘要： A non-volatile memory device comprises a memory cell region including a plurality of cell transistors, a first-type semiconductor substrate including a peripheral circuit region including circuits configured to control the plurality of cell transistors, and a plurality of pass transistors on the peripheral circuit region of the semiconductor substrate, wherein the peripheral circuit region includes a first region and a second region which are doped to a depth at an upper portion of the semiconductor substrate while being insulated from each other by an implant region, wherein the first region is a second type different from the first type, and includes a first doped region, and a first well region beneath the first doped region and configured to have a higher doping concentration than the first doped region, wherein the second region is the first type, and includes a second doped region, and a second well region beneath the second doped region and configured to have a higher doping concentration than the second doped region, wherein a first pass transistor on the first region from among the plurality of pass transistors is connected to a string selection line or a ground selection transistor, wherein a second pass transistor on the second region from among the plurality of pass transistors is connected to a word line, wherein a positive voltage or a negative voltage is configured to be applied to the second well region during operation of the second pass transistor.

6. 发明申请

US20210143172A1 SEMICONDUCTOR DEVICE INCLUDING VERTICAL MEMORY STRUCTURE 有权
公开(公告)号：US20210143172A1
公开(公告)日：2021-05-13
申请号：US17036034
申请日：2020-09-29
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Janggn YUN , Jaeduk LEE , Dongwhee KWON
IPC分类号： H01L27/11582 , H01L27/24 , H01L27/11556 , H01L23/535
摘要： A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.

7. 发明申请

US20210043649A1 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20210043649A1
公开(公告)日：2021-02-11
申请号：US16936888
申请日：2020-07-23
申请人： Samsung Electronics Co., Ltd.
发明人： Sangyong PARK , Hyunseok NA , Jaeduk LEE
IPC分类号： H01L27/11582 , H01L27/11556
摘要： An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

8. 发明公开

US20240297117A1 SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 审中-公开
公开(公告)号：US20240297117A1
公开(公告)日：2024-09-05
申请号：US18519551
申请日：2023-11-27
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hyunjung KIM , Sejun PARK , Jaeduk LEE , Eiwhan JUNG
IPC分类号： H01L23/528 , H01L23/522 , H01L25/065 , H01L29/423 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC分类号： H01L23/5283 , H01L23/5226 , H01L25/0652 , H01L29/42328 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/06506
摘要： A semiconductor device includes a first semiconductor structure including a substrate, circuit devices on the substrate, and circuit interconnection lines on the circuit devices; and a second semiconductor structure on the first semiconductor structure and having a first region and a second region, wherein the second semiconductor structure includes gate electrodes; first channel structures in the first region; second channel structures in the first region; and contact plugs in the second region, the gate electrodes include first gate electrodes having a first thickness in the vertical direction in the first region and second gate electrodes having a second thickness in the vertical direction greater than the first thickness in the first region, and the second gate electrodes are commonly connected to one of the contact plugs.

9. 发明公开

US20240130133A1 VERTICAL NONVOLATILE MEMORY DEVICE HAVING HYDROGEN DIFFUSION BARRIER LAYER AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20240130133A1
公开(公告)日：2024-04-18
申请号：US18446911
申请日：2023-08-09
申请人： Samsung Electronics Co., Ltd.
发明人： Sohyeon LEE , Seongpil CHANG , Sea Hoon LEE , Jaeduk LEE , Tackhwi LEE
IPC分类号： H10B43/40 , H01L23/528 , H10B41/27 , H10B41/40 , H10B43/27
CPC分类号： H10B43/40 , H01L23/5283 , H10B41/27 , H10B41/40 , H10B43/27
摘要： A vertical nonvolatile memory device may include a peripheral circuit portion including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer above the peripheral circuit portion; a first insulating layer above the first hydrogen diffusion barrier layer; a common source line layer above the first insulating layer; a second hydrogen diffusion barrier layer above the first insulating layer; and a memory cell stack structure above the common source line layer and the second hydrogen diffusion barrier layer.

10. 发明申请

US20200350326A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20200350326A1
公开(公告)日：2020-11-05
申请号：US16668222
申请日：2019-10-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Janggn YUN , Jaeduk LEE
IPC分类号： H01L27/11548 , H01L27/11556 , H01L27/11582 , H01L23/522 , H01L27/11519 , H01L27/11565 , H01L27/11575
摘要： A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.

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