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    • 2. 发明授权
    • Display apparatus
    • 显示装置
    • US09542874B2
    • 2017-01-10
    • US14280529
    • 2014-05-16
    • SAMSUNG DISPLAY CO., LTD.
    • Suhyeong ParkUnggyu MinYoung-Soo YoonSangik Lee
    • G06F3/038G09G3/20G09G3/36
    • G09G3/20G09G3/3614G09G3/3688G09G2310/0254G09G2310/0275G09G2310/0281G09G2310/0297G09G2320/0223G09G2330/08
    • A display apparatus includes: a plurality of pixels coupled to gate lines and to data lines configured to cross the gate lines, a gate driver configured to apply gate signals to the gate lines, a first data driver configured to apply first data voltages to first signal lines, a first DEMUX part configured to selectively couple the first signal lines to the data lines, a second data driver configured to apply second data voltages to second signal lines positioned to correspond to the first signal lines, and a second DEMUX part positioned to face the first DEMUX part such that the pixels are positioned between the first and second DEMUX parts, the second DEMUX part configured to couple the second signal lines to the data lines, which are not coupled to the first signal lines. Each of the first data voltages has a polarity opposite to a polarity of a corresponding second data voltage of the second data voltages.
    • 显示装置包括:耦合到栅极线和配置成跨越栅极线的数据线的多个像素,被配置为向栅极线施加栅极信号的栅极驱动器,被配置为将第一数据电压施加到第一信号的第一数据驱动器 线路,被配置为选择性地将第一信号线耦合到数据线的第一DEMUX部分,被配置为将第二数据电压施加到与第一信号线对应的第二信号线的第二数据驱动器,以及定位成面对的第二DEMUX部分 第一DEMUX部分,使得像素位于第一和第二DEMUX部分之间,第二DEMUX部分被配置为将第二信号线耦合到未耦合到第一信号线的数据线。 每个第一数据电压具有与第二数据电压的对应的第二数据电压的极性相反的极性。
    • 5. 发明申请
    • DISPLAY APPARATUS
    • 显示设备
    • US20150145843A1
    • 2015-05-28
    • US14280529
    • 2014-05-16
    • SAMSUNG DISPLAY CO., LTD.
    • Suhyeong ParkUnggyu MinYoung-Soo YoonSangik Lee
    • G09G3/20
    • G09G3/20G09G3/3614G09G3/3688G09G2310/0254G09G2310/0275G09G2310/0281G09G2310/0297G09G2320/0223G09G2330/08
    • A display apparatus includes: a plurality of pixels coupled to gate lines and to data lines configured to cross the gate lines, a gate driver configured to apply gate signals to the gate lines, a first data driver configured to apply first data voltages to first signal lines, a first DEMUX part configured to selectively couple the first signal lines to the data lines, a second data driver configured to apply second data voltages to second signal lines positioned to correspond to the first signal lines, and a second DEMUX part positioned to face the first DEMUX part such that the pixels are positioned between the first and second DEMUX parts, the second DEMUX part configured to couple the second signal lines to the data lines, which are not coupled to the first signal lines. Each of the first data voltages has a polarity opposite to a polarity of a corresponding second data voltage of the second data voltages.
    • 显示装置包括:耦合到栅极线和配置成跨越栅极线的数据线的多个像素,被配置为向栅极线施加栅极信号的栅极驱动器,被配置为将第一数据电压施加到第一信号的第一数据驱动器 线路,被配置为选择性地将第一信号线耦合到数据线的第一DEMUX部分,被配置为将第二数据电压施加到与第一信号线对应的第二信号线的第二数据驱动器,以及定位成面对的第二DEMUX部分 第一DEMUX部分,使得像素位于第一和第二DEMUX部分之间,第二DEMUX部分被配置为将第二信号线耦合到未耦合到第一信号线的数据线。 每个第一数据电压具有与第二数据电压的对应的第二数据电压的极性相反的极性。
    • 10. 发明授权
    • Gate driving circuit and display apparatus having the same
    • 栅极驱动电路及其显示装置
    • US08816728B2
    • 2014-08-26
    • US14057354
    • 2013-10-18
    • Samsung Display Co., Ltd.
    • Soo-Wan YoonYeong-Keun KwonJi-Sun KimYoung-Soo YoonChong-Chui Chai
    • H03K3/00
    • H03K3/012G09G3/3674G09G2310/0286G09G2330/021G11C19/184G11C19/28
    • A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.
    • 栅极驱动电路包括上拉控制部分,上拉部分,携带部分,第一下拉部分和第二下拉部分。 上拉控制部分将来自前一级的进位信号应用于第一节点。 上拉部分基于时钟信号输出第N个栅极输出信号。 进位部分响应于施加到第一节点的信号,基于时钟信号输出第N个进位信号。 第一下拉部分包括彼此串联连接的多个晶体管。 第一下拉部分响应于下一级的进位信号将第一节点处的信号拉低至第二截止电压。 第二下拉部分响应于下一级的进位信号将第N栅极输出信号拉低至第一关断电压。