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    • 1. 发明申请
    • LIQUID CRYSTAL DISPLAY
    • 液晶显示器
    • US20150205172A1
    • 2015-07-23
    • US14479527
    • 2014-09-08
    • Samsung Display Co., Ltd.
    • Kyoung Ju SHIN
    • G02F1/1343G02F1/1362
    • G02F1/134363G02F2001/134318
    • A liquid crystal display includes a first substrate, a gate line disposed on an upper portion of the first substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode and defines a contact hole which exposes a part of the drain electrode, a common electrode provided at an upper portion of the passivation layer and having a planar structure, a pixel electrode electrically connected to the drain electrode through the contact hole and including a plurality of pixel branch electrodes, and a second substrate corresponding to the first substrate, where an opening is defined in the common electrode at a position which corresponds to a middle region of the plurality of pixel branch electrodes.
    • 液晶显示器包括第一基板,设置在第一基板的上部的栅极线,设置在栅极线上的栅极绝缘层,设置在栅极绝缘层上的半导体层,设置在数据线和漏极上的 在所述半导体层上具有覆盖所述数据线和所述漏电极并且限定露出所述漏电极的一部分的接触孔的钝化层,设置在所述钝化层的上部并具有平面结构的公共电极, 像素电极,其通过接触孔电连接到漏电极,并且包括多个像素分支电极,以及对应于第一基板的第二基板,其中在公共电极中限定一个开口,该开口对应于 多个像素分支电极。
    • 8. 发明申请
    • GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME
    • 门驱动电路和包括它的显示装置
    • US20160293094A1
    • 2016-10-06
    • US15048979
    • 2016-02-19
    • Samsung Display Co., Ltd.
    • Jun Hyun PARKSung Hwan KIMSe Young SONGKyoung Ju SHIN
    • G09G3/20H03K17/687
    • H03K17/6871G09G3/20G09G2310/0267G09G2310/0286G11C19/184G11C19/28
    • A gate driving circuit includes: a plurality of stages configured to output a plurality of gate signals, wherein an Nth stage of the plurality of stages includes: an output pull-up unit including a control electrode connected to a first node, wherein the output pull-up unit is configured to increase an electric potential at the first node and is further configured to receive a clock signal and to output a gate signal of the Nth stage; a control node pull-up unit configured to charge the first node according to an (N−1)th control signal and an (N−2)th control signal; a control node pull-down unit configured to discharge a voltage of the first node as a first low voltage according to an (N+1)th control signal; and an output pull-down unit configured to discharge a gate signal of the Nth stage as the first low voltage according to the (N+1)th control signal.
    • 栅极驱动电路包括:多个级,被配置为输出多个栅极信号,其中所述多个级的第N级包括:输出上拉单元,包括连接到第一节点的控制电极,其中所述输出拉 所述单元被配置为增加所述第一节点处的电位,并且还被配置为接收时钟信号并输出​​所述第N级的门信号; 控制节点上拉单元,被配置为根据第(N-1)个控制信号和第(N-2)个控制信号对所述第一节点充电; 控制节点下拉单元,被配置为根据第(N + 1)个控制信号将第一节点的电压作为第一低电压放电; 以及输出下拉单元,被配置为根据第(N + 1)个控制信号,将第N级的栅极信号作为第一低电压放电。