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1. 发明授权

US07485581B2 Device with gaps for capacitance reduction 有权
标题翻译：具有间隙的器件，用于降低电容
公开(公告)号：US07485581B2
公开(公告)日：2009-02-03
申请号：US11291411
申请日：2005-11-30
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： H01L21/302 , H01L21/461 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76843 , H01L23/4821 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
摘要翻译：提供一种降低半导体器件之间的电容的方法。在电介质层中形成多个接触结构。形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。掩模特征的宽度随着侧壁沉积而收缩。间隙通过侧壁沉积蚀刻到介电层中。间隙封闭以形成间隙中的凹坑。

2. 发明申请

US20120205819A1 DEVICE WITH GAPS FOR CAPACITANCE REDUCTION 有权
标题翻译：具有电容降低功能的器件
公开(公告)号：US20120205819A1
公开(公告)日：2012-08-16
申请号：US13457147
申请日：2012-04-26
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76843 , H01L23/4821 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
摘要翻译：提供一种降低半导体器件之间的电容的方法。在电介质层中形成多个接触结构。形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。掩模特征的宽度随着侧壁沉积而收缩。间隙通过侧壁沉积蚀刻到介电层中。间隙封闭以形成间隙中的凹坑。

3. 发明授权

US08172980B2 Device with self aligned gaps for capacitance reduction 有权
标题翻译：具有自对准间隙的器件，用于降低电容
公开(公告)号：US08172980B2
公开(公告)日：2012-05-08
申请号：US12202043
申请日：2008-08-29
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00
CPC分类号： H01L21/7682 , H01J37/32623 , H01J37/32633 , H01J37/32642 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了用于降低半导体器件布线之间的电容的方法。在电介质层上形成牺牲层。多个特征被蚀刻到牺牲层和电介质层中。功能填充填充材料。去除牺牲层，使得填充材料的部分保持暴露在电介质层的表面之上，其中空间位于填充材料的暴露部分之间，其中空间在先前被牺牲层占据的区域中。填充材料部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将间隙蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

4. 发明授权

US07432189B2 Device with self aligned gaps for capacitance reduction 有权
标题翻译：具有自对准间隙的器件，用于降低电容
公开(公告)号：US07432189B2
公开(公告)日：2008-10-07
申请号：US11291672
申请日：2005-11-30
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01J37/32623 , H01J37/32633 , H01J37/32642 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了用于降低半导体器件布线之间的电容的方法。在电介质层上形成牺牲层。多个特征被蚀刻到牺牲层和电介质层中。功能填充填充材料。去除牺牲层，使得填充材料的部分保持暴露在电介质层的表面之上，其中空间位于填充材料的暴露部分之间，其中空间在先前被牺牲层占据的区域中。填充材料部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将间隙蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

5. 发明授权

US08866202B2 Device with gaps for capacitance reduction 有权
标题翻译：具有间隙的器件，用于降低电容
公开(公告)号：US08866202B2
公开(公告)日：2014-10-21
申请号：US13457147
申请日：2012-04-26
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： H01L21/70 , H01L23/48 , H01L23/52 , H01L21/768 , H01L23/482 , H01L21/033 , H01L21/311
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76843 , H01L23/4821 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
摘要翻译：提供一种降低半导体器件之间的电容的方法。在电介质层中形成多个接触结构。形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。掩模特征的宽度随着侧壁沉积而收缩。间隙通过侧壁沉积蚀刻到介电层中。间隙封闭以形成间隙中的凹坑。

6. 发明授权

US08187412B2 Apparatus for providing device with gaps for capacitance reduction 有权
标题翻译：用于为器件提供间隙以减少电容的装置
公开(公告)号：US08187412B2
公开(公告)日：2012-05-29
申请号：US12341568
申请日：2008-12-22
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76843 , H01L23/4821 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
摘要翻译：提供一种用于降低半导体器件之间的电容的方法。在电介质层中形成多个接触结构。形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。掩模特征的宽度随着侧壁沉积而收缩。间隙通过侧壁沉积蚀刻到介电层中。间隙封闭，形成缝隙。

7. 发明申请

US20090140380A1 DEVICE WITH GAPS FOR CAPACITANCE REDUCTION 有权
标题翻译：具有电容降低功能的器件
公开(公告)号：US20090140380A1
公开(公告)日：2009-06-04
申请号：US12341568
申请日：2008-12-22
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： H01L23/532 , H01L21/20
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76843 , H01L23/4821 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
摘要翻译：提供一种降低半导体器件之间的电容的方法。在电介质层中形成多个接触结构。形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。掩模特征的宽度随着侧壁沉积而收缩。间隙通过侧壁沉积蚀刻到介电层中。间隙封闭以形成间隙中的凹坑。

8. 发明授权

US07682479B2 Fin structure formation 有权
标题翻译：鳍结构形成
公开(公告)号：US07682479B2
公开(公告)日：2010-03-23
申请号：US11830761
申请日：2007-07-30
申请人： Zhi-Song Huang , S. M. Reza Sadjadi
发明人： Zhi-Song Huang , S. M. Reza Sadjadi
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00
CPC分类号： H01L21/0337 , H01L21/0338
摘要： A method for forming fin structures is provided. Sacrificial structures are provided on a substrate. Fin structures are formed on the sides of the sacrificial structures. The forming of the fin structures comprises a plurality of cycles, wherein each cycle comprises a fin deposition phase and a fin profile shaping phase. The sacrificial structure is removed.
摘要翻译：提供了一种用于形成翅片结构的方法。牺牲结构设置在基板上。翅片结构形成在牺牲结构的侧面上。翅片结构的形成包括多个循环，其中每个循环包括翅片沉积阶段和翅片轮廓成形阶段。牺牲结构被去除。

9. 发明申请

US20080314521A1 DEVICE WITH SELF ALIGNED GAPS FOR CAPACITANCE REDUCTION 有权
标题翻译：具有自适应GAPS以减少电容的装置
公开(公告)号：US20080314521A1
公开(公告)日：2008-12-25
申请号：US12202043
申请日：2008-08-29
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： H01L21/306 , C23C16/00
CPC分类号： H01L21/7682 , H01J37/32623 , H01J37/32633 , H01J37/32642 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了用于降低半导体器件布线之间的电容的方法。在电介质层上形成牺牲层。多个特征被蚀刻到牺牲层和电介质层中。功能填充填充材料。去除牺牲层，使得填充材料的部分保持暴露在电介质层的表面之上，其中空间位于填充材料的暴露部分之间，其中空间在先前被牺牲层占据的区域中。填充材料部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将间隙蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

10. 发明授权

US07264743B2 Fin structure formation 有权
标题翻译：鳍结构形成
公开(公告)号：US07264743B2
公开(公告)日：2007-09-04
申请号：US11338464
申请日：2006-01-23
申请人： Zhi-Song Huang , S. M. Reza Sadjadi
发明人： Zhi-Song Huang , S. M. Reza Sadjadi
IPC分类号： C03C25/68
CPC分类号： H01L21/0337 , H01L21/0338
摘要： A method for forming fin structures is provided. Sacrificial structures are provided on a substrate. Fin structures are formed on the sides of the sacrificial structures. The forming of the fin structures comprises a plurality of cycles, wherein each cycle comprises a fin deposition phase and a fin profile shaping phase. The sacrificial structure is removed.
摘要翻译：提供了一种用于形成翅片结构的方法。牺牲结构设置在基板上。翅片结构形成在牺牲结构的侧面上。翅片结构的形成包括多个循环，其中每个循环包括翅片沉积阶段和翅片轮廓成形阶段。牺牲结构被去除。

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