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1. 发明申请

US20080107885A1 High-capacity, low-leakage multilayer dielectric stacks 审中-公开
标题翻译：大容量，低漏电多层电介质叠层
公开(公告)号：US20080107885A1
公开(公告)日：2008-05-08
申请号：US11827555
申请日：2007-07-12
申请人： S. Alpay , Jospeh Mantese , Shan Zhong
发明人： S. Alpay , Jospeh Mantese , Shan Zhong
IPC分类号： B32B9/00 , H01L21/00
CPC分类号： H01L28/56
摘要： The present disclosure is directed to an exemplary method for designing, implementing, and making a high capacity low leakage multilayer stack for various electronic applications. In a particular embodiment, the multilayer stack is made up of a dielectric/ferroelectric/dielectric trilayer. This configuration has shown to have giant dielectric permittivity which is much higher than conventional gate dielectrics. The DE/FE interlayer exhibits strong interlayer coupling, yielding desired properties. In order to prevent leakage and loss while maintaining high capacity, certain parameters of each layer must exist. The present disclosure describes a method of quantitatively achieving these parameters through correlating critical fraction with dielectric constant. Moreover, this method can be used for scalability of electronic materials.
摘要翻译：本公开涉及用于设计，实施和制造用于各种电子应用的高容量低泄漏多层堆叠的示例性方法。在特定实施例中，多层叠层由介电/铁电/介质三层组成。该配置已经显示出具有比常规栅极电介质高得多的大介电常数。 DE / FE夹层表现出强的层间耦合，产生所需的性能。为了在保持高容量的同时防止泄漏和损耗，必须存在每层的某些参数。本公开描述了通过将关键分数与介电常数相关联来定量地实现这些参数的方法。此外，该方法可用于电子材料的可扩展性。

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